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參數(shù)資料
| 型號(hào)： | TNETA1556 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 155.52-Mbit/S Clock-Recovery Device(155.52-MBIT/S時(shí)鐘恢復(fù)裝置) |
| 中文描述： | 155.52 - Mbit / s的時(shí)鐘恢復(fù)裝置（155.52 - Mbit / s的時(shí)鐘恢復(fù)裝置） |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 216K |
| 代理商： | TNETA1556 |
TNETA1556
155.52-MBIT/S CLOCK-RECOVERY DEVICE
SDNS015C – FEBRUARY 1994 – REVISED JUNE 1995
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
jitter tolerance (continued)
0.1
0.01
10
100
1k
10k
P
1
10
100
1000
100k
1M
10M
f – Frequency – Hz
TNETA1556
Bellcore
I
Figure 2. Jitter Tolerance (worst case)
transitionless bit periods
The SONET/SDH specifications do not use a line code that limits the number of transitionless bit periods in a
bit stream to a specific number. Instead, a scrambler is used to provide some randomization of the line signal.
As long as the output data stream does not match the output of the scrambler, this technique works fairly well.
However, it is possible for the scrambled data stream to contain a large number of transitionless bit periods,
depending upon the data being transmitted. It is important that the clock-recovery device handle large numbers
of transitionless bit periods without causing a bit error. Figures 3 and 4 show the results of tests conducted on
the TNETA1556 for transitionless bit periods. The y-axis shows the number of transitionless bit periods that the
devices can accept before a bit error is recorded on the bit-error rate tester.
P
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