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TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Table 3-17. EMAC and GPIO3V Multiplexed Pins
(continued)
GPIO
GPIO3V[4]
GPIO3V[5]
GPIO3V[6]
GPIO3V[7]
GPIO3V[8]
GPIO3V[9]
GPIO3V[10]
GPIO3V[11]
GPIO3V[12]
GPIO3V[13]
GPIO3V[14]
GPIO3V[15]
GPIO3V[16]
EMAC
TXD[1]
TXD[2]
TXD[3]
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXCLK
RXDV
RXER
CRS
MDIO
MDCLK
3.5.6.2
VPBE (LCD) and GPIO Pin Multiplexing
The LCD controller in the VPSS requires multiplex control bit settings for certain modes of operation. Bits
within the PinMux0 register, which select between the LCD control signal function and GPIO, are
summarized in
Table 3-18
.
Table 3-18. VPBE (LCD) and GPIO Pin Multiplexing
PINMUX0
MULTIPLEXED PINS
REGISTER FIELDS
LFLDEN
-
-
0
1
LOEEN
0
1
-
-
LCD_FIELD/B0/GPIO[3]
LCD_OE/GPIO[0]
-
-
B0/GPIO[3]
(1)
LCD_FIELD
GPIO[0]
LCD_OE
-
-
(1)
Depends on RGB888 bit setting, see
Table 3-19
VPBE (RGB666 and RGB888) and GPIO Pin Multiplexing
3.5.6.3
Use of the RGB666 and RGB888 modes of the VPBE requires enabling RGB pins as shown in
Table 3-19
and
Table 3-20
. Enabling PWM2, PWM1, and LCD functionality overrides the the RGB modes. RGB666
interface pin functionality requires setting the RGB666 PINMUX0 Register bit field to ‘1’ and PINMUX1
Register bit fields PWM2 and PWM1 to ‘0’. Proper RGB888 interface operation requires setting PINMUX0
Register bit field RGB888 to ‘1’ and bit fields PWM2, PWM1, and LFLDEN must be set to ‘0’.
Table 3-19. VPBE (RGB666, RGB888, and LCD), and GPIO Pin Multiplexing
PINMUX0 AND PINMUX1 REGISTER BIT FIELDS
MULTIPLEXED PINS
PWM1/
R2/
GPIO[46]
GPIO[46]
-
PWM1
-
R2
R2
PWM2/
B2/
GPIO[47]
GPIO[47]
-
-
PWM2
B2
B2
LCD_FIELD/
B0/
GPIO[3]
GPIO[3]
LCD_FIELD
-
-
GPIO[3]
B0
RGB888
RGB666
PWM2
PWM1
LFLDEN
0
-
-
-
0
1
0
-
-
-
1
-
0
-
-
1
0
0
0
-
1
-
0
0
0
1
-
-
0
0
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