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TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Table 6-67. UART1 Register Descriptions (continued)
HEX ADDRESS RANGE
0x01C2 0408
0x01C2 0408
0x01C2 040C
0x01C2 0410
0x01C2 0414
0x01C2 0418
0x01C2 041C
0x01C2 0420
0x01C2 0424
0x01C2 0428
0x01C2 042C
0x01C2 0430
0x01C2 0434 - 0x01C2 07FF
ACRONYM
IIR
FCR
LCR
MCR
LSR
-
-
DLL
DLH
PID1
PID2
PWREMU_MGMT
-
REGISTER NAME
UART1 Interrupt Identification Register (Read Only)
UART1 FIFO Control Register (Write Only)
UART1 Line Control Register
UART1 Modem Control Register
UART1 Line Status Register
Reserved
Reserved
UART1 Divisor Latch (LSB)
UART1 Divisor Latch (MSB)
Peripheral Identification Register 1
Peripheral Identification Register 2
UART1 Power and Emulation Management Register
Reserved
Table 6-68. UART2 Register Descriptions
HEX ADDRESS RANGE
0x01C2 0800
0x01C2 0800
0x01C2 0804
0x01C2 0808
0x01C2 0808
0x01C2 080C
0x01C2 0810
0x01C2 0814
0x01C2 0818
0x01C2 081C
0x01C2 0820
0x01C2 0824
0x01C2 0828
0x01C2 082C
0x01C2 0830
0x01C2 0834 - 0x01C2 0BFF
ACRONYM
RBR
THR
IER
IIR
FCR
LCR
MCR
LSR
-
-
DLL
DLH
PID1
PID2
PWREMU_MGMT
-
REGISTER NAME
UART2 Receiver Buffer Register (Read Only)
UART2 Transmitter Holding Register (Write Only)
UART2 Interrupt Enable Register
UART2 Interrupt Identification Register (Read Only)
UART2 FIFO Control Register (Write Only)
UART2 Line Control Register
UART2 Modem Control Register
UART2 Line Status Register
Reserved
Reserved
UART2 Divisor Latch (LSB)
UART2 Divisor Latch (MSB)
Peripheral Identification Register 1
Peripheral Identification Register 2
UART2 Power and Emulation Management Register
Reserved
Peripheral and Electrical Specifications
186
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