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6.11
ATA/CF
6.11.1 ATA/CF Peripheral Register Description(s)
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
The ATA/CF peripheral supports the following features:
PIO, multiword DMA, and Ultra ATA 33/66
Up to mode 4 timings on PIO mode
Up to mode 2 timings on multiword DMA
Up to mode 4 timings on Ultra ATA
Programmable timing parameters
Supports TrueIDE mode for Compact Flash
In addition, the Host IDE Controller supports multiword DMA transfers between external IDE/ATAPI
devices and a system memory bus interface.
The ATA registers are shown in
Table 6-38
.
Table 6-38. ATA Register Memory Map
HEX ADDRESS RANGE ACRONYM
REGISTER NAME
ATA Bus Master Interface DMA Engine Registers
Primary IDE Channel DMA Control Register
Primary IDE Channel DMA Status Register
Primary IDE Channel DMA Descriptor Table Pointer Register
0x01C6 6000
0x01C6 6002
0x01C6 6004
0x01C6 6008
0x01C6 600A
0x01C6 600C
BMICP
BMISP
BMIDTP
-
-
-
Reserved
ATA Configuration Registers
Primary IDE Channel Timing Register
0x01C6 6040
0x01C6 6042
0x01C6 6044
0x01C6 6045
0x01C6 6047
0x01C6 6048
0x01C6 604A
0x01C6 6050
0x01C6 6054
0x01C6 6058
0x01C6 605C
0x01C6 6060
0x01C6 6064
0x01C6 6068
0x01C6 606C
0x01C6 6070
0x01C6 6074
0x01C6 6078
0x01C6 607C - 0x01C6
67FF
IDETIMP
-
-
-
IDESTAT
UDMACTL
-
MISCCTL
REGSTB
REGRCVR
DATSTB
DATRCVR
DMASTB
DMARCVR
UDMASTB
UDMATRP
UDMATENV
IORDYTMP
-
Reserved
IDE Controller Status Register
Ultra-DMA Control Register
Reserved
Miscellaneous Control Register
Task File Register Strobe Timing Register
Task File Register Recovery Timing Register
Data Register Access PIO Strobe Timing Register
Data Register Access PIO Recovery Timing Register
Multiword DMA Strobe Timing Register
Multiword DMA Recovery Timing Register
Ultra-DMA Strobe Timing Register
Ultra-DMA Ready-to-Pause Timing Register
Ultra-DMA Timing Envelope Register
Primary IO Ready Timer Configuration Register
Reserved
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Peripheral and Electrical Specifications
141