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DDR_CLK0
1
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Table 6-36. DDR2 Memory Controller Registers (continued)
HEX ADDRESS RANGE
0x2000 00C8
0x2000 00CC
0x2000 00D0 - 0x2000 00E3
0x2000 00E4
0x2000 00E8 - 0x2000 00EF
0x2000 00F0
0x2000 00F4 - 0x2000 7FFF
ACRONYM
IMSR
IMCR
-
DDRPHYCR
-
VTPIOCR
-
REGISTER NAME
Interrupt Mask Set Register
Interrupt Mask Clear Register
Reserved
DDR PHY Control Register
Reserved
VTP IO Control Register
Reserved
6.10.2.1
DDR2 Memory Controller Electrical Data/Timing
The
Implementing DDR2 PCB Layout on the DM644x DMSoC
application report (literature number
SPRAAC5) specifies a complete DDR2 interface solution for the DM6443 as well as a list of compatible
DDR2 devices. TI has performed the simulation and system characterization to ensure all DDR2 interface
timings in this solution are met.
TI only supports board designs that follow the guidelines outlined in the
Implementing DDR2 PCB Layout
on the DM644x DMSoC
application report (literature number
SPRAAC5
).
Table 6-37. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory
Controller
(1)(2)
(see
Figure 6-25
)
-594
NO.
PARAMETER
UNIT
MIN
MAX
1
t
c(DDR_CLK0)
DDR_CLK0 cycle time = 2 x PLL2 - SYSCLK2 cycle time.
The PLL2 Controller
must
be programmed such that the resulting DDR_CLK0 clock frequency is within the specified range.
Cycle time, DDR_CLK0
6
8
ns
(1)
(2)
Figure 6-25. DDR2 Memory Controller Clock Timing
140
Peripheral and Electrical Specifications
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