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TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Table 2-3. Memory Map Summary
START
ADDRESS
END
SIZE
(Bytes)
EDMA/
ARM
C64x+
HPI
VPSS
ADDRESS
PERIPHERAL
0x0000 0000
0x0000 1FFF
8K
ARM RAM0 (Instruction)
0x0000 2000
0x0000 3FFF
8K
ARM RAM1 (Instruction)
Reserved
Reserved
0x0000 4000
0x0000 5FFF
8K
ARM ROM (Instruction)
0x0000 6000
0x0000 7FFF
8K
Reserved
0x0000 8000
0x0000 9FFF
8K
ARM RAM0 (Data)
ARM RAM0
ARM RAM0
0x0000 A000
0x0000 BFFF
8K
ARM RAM1 (Data)
Reserved
ARM RAM1
ARM RAM1
0x0000 C000
0x0000 DFFF
8K
ARM ROM (Data)
ARM ROM
ARM ROM
0x0000 E000
0x0000 FFFF
8K
0x0001 0000
0x000F FFFF
960K
0x0010 0000
0x001F FFFF
1M
0x0020 0000
0x007F FFFF
6M
0x0080 0000
0x0080 FFFF
64K
L2 RAM/Cache
0x0081 0000
0x00E0 7FFF
6112K
Reserved
Reserved
0x00E0 8000
0x00E0 FFFF
32K
L1P Cache
0x00E1 0000
0x00F0 3FFF
976K
Reserved
Reserved
Reserved
0x00F0 4000
0x00F0 FFFF
48K
L1D RAM
0x00F1 0000
0x00F1 7FFF
32K
L1D Cache
0x00F1 8000
0x017F FFFF
9120K
Reserved
0x0180 0000
0x01BB FFFF
3840K
0x01BC 0000
0x01BC 0FFF
4K
ARM ETB Memory
0x01BC 1000
0x01BC 17FF
2K
ARM ETB Registers
CFG Space
0x01BC 1800
0x01BC 18FF
256
ARM IceCrusher
0x01BC 1900
0x01BF FFFF
255744
Reserved
Reserved
0x01C0 0000
0x01FF FFFF
4M
CFG Bus Peripherals
CFG Bus Peripherals
CFG Bus Peripherals
CFG Bus Peripherals
(1)
0x0200 0000
0x09FF FFFF
128M
EMIFA (Code and Data)
EMIFA (Data)
EMIFA (Data)
0x0A00 0000
0x0BFF FFFF
32M
Reserved
Reserved
0x0C00 0000
0x0FFF FFFF
64M
VLYNQ (Remote)
Reserved
VLYNQ (Remote)
0x1000 0000
0x1000 7FFF
32K
Reserved
0x1000 8000
0x1000 9FFF
8K
ARM RAM0
ARM RAM0
0x1000 A000
0x1000 BFFF
8K
ARM RAM1
ARM RAM1
0x1000 C000
0x1000 DFFF
8K
ARM ROM
ARM ROM
Reserved
0x1000 E000
0x1000 FFFF
8K
0x1001 0000
0x110F FFFF
17344K
Reserved
Reserved
Reserved
0x1110 0000
0x111F FFFF
1M
0x1120 0000
0x117F FFFF
6M
0x1180 0000
0x1180 FFFF
64K
L2 RAM/Cache
L2 RAM/Cache
L2 RAM/Cache
0x1181 0000
0x11E0 7FFF
6112K
Reserved
Reserved
Reserved
0x11E0 8000
0x11E0 FFFF
32K
L1P Cache
L1P Cache
L1P Cache
0x11E1 0000
0x11F0 3FFF
976K
Reserved
Reserved
Reserved
0x11F0 4000
0x11F0 FFFF
48K
L1D RAM
L1D RAM
L1D RAM
0x11F1 0000
0x11F1 7FFF
32K
L1D RAM/Cache
L1D RAM/Cache
L1D RAM/Cache
0x11F1 8000
0x1FFF FFFF
241M-
32K
Reserved
Reserved
Reserved
0x2000 0000
0x2000 7FFF
32K
DDR2 Control Registers
DDR2 Control Registers
DDR2 Control Registers
DDR2 Control Registers
0x2000 8000
0x41FF FFFF
544M-32k Reserved
Reserved
Reserved
0x4200 0000
(2)
0x4FFF FFFF
224M
Reserved
EMIFA/VLYNQ Shadow
EMIFA/VLYNQ Shadow
Reserved
0x5000 0000
0x7FFF FFFF
768M
Reserved
Reserved
Reserved
0x8000 0000
0x8FFF FFFF
256M
DDR2
DDR2
DDR2
DDR2
DDR2
0x9000 0000
0xFFFF FFFF
1792M
Reserved
Reserved
Reserved
Reserved
Reserved
(1)
HPI's access to the configuration bus peripherals is limited to the power and sleep controller registers, PLL1 and PLL2 registers, and
HPI configuration registers.
EMIFA shadow memory started a 0x4200 0000 is physically the same memory as location 0x0200 0000. Memory range 0x200 0000
through 0x09FF FFFF should only be used by C64x+ for data accesses. Memory range 0x4200 0000 through 0x4FFF FFFF can be
used by C64x+ for both code execution and data accesses.
(2)
Device Overview
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