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6.8.2
GPIO Peripheral Input/Output Electrical Data/Timing
GPIx
GPOx
4
3
2
1
6.8.3
GPIO Peripheral External Interrupts Electrical Data/Timing
EXT_INTx
2
1
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Table 6-26. Timing Requirements for GPIO Inputs
(1)
(see
Figure 6-19
)
-594
NO.
UNIT
MIN
52
52
MAX
1
2
t
w(GPIH)
t
w(GPIL)
Pulse duration, GPIx high
Pulse duration, GPIx low
ns
ns
(1)
The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have DM6443 recognize
the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow DM6443 enough time to
access the GPIO register through the internal bus.
Table 6-27. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see
Figure 6-19
)
-594
MIN
26
(1)
26
(1)
NO.
PARAMETER
UNIT
MAX
3
4
t
w(GPOH)
t
w(GPOL)
Pulse duration, GPOx high
Pulse duration, GPOx low
ns
ns
(1)
This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
Figure 6-19. GPIO Port Timing
Table 6-28. Timing Requirements for External Interrupts
(1)
(see
Figure 6-20
)
-594
MIN
52
52
NO.
UNIT
MAX
1
2
t
w(ILOW)
t
w(IHIGH)
The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have DM6443recognize the
GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow DM6443 enough time to
access the GPIO register through the internal bus.
Width of the external interrupt pulse low
Width of the external interrupt pulse high
ns
ns
(1)
Figure 6-20. GPIO External Interrupt Timing
120
Peripheral and Electrical Specifications
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