參數(shù)資料
型號: TMS470R1B768PGEQR
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁數(shù): 9/49頁
文件大?。?/td> 552K
代理商: TMS470R1B768PGEQR
Interrupt Priority (IEM to CIM)
www.ti.com ......................................................................................................................................................... SPNS108B – AUGUST 2005 – REVISED MAY 2008
Interrupt requests originating from the B768 peripheral modules (i.e., SPI1, SPI2, or SPI3; SCI1 or SCI2; HECC1
or HECC2; RTI; etc.) are assigned to channels within the 48-channel interrupt expansion module (IEM) where,
via programmable register mapping, these channels are then mapped to the 32-channel central interrupt
manager (CIM) portion of the SYS module.
Programming multiple interrupt sources in the IEM to the same CIM channel effectively shares the CIM channel
between sources.
The CIM request channels are maskable so that individual channels can be selectively disabled. All interrupt
requests can be programmed in the CIM to be of either type:
Fast interrupt request (FIQ)
Normal interrupt request (IRQ)
The CIM prioritizes interrupts. The precedence of request channels decrease with ascending channel order in the
CIM (0 [highest] and 31 [lowest] priority). For IEM-to-CIM default mapping, channel priorities, and their
associated modules, see Table 7.
Table 7. Interrupt Priority (IEM and CIM)
DEFAULT CIM INTERRUPT
MODULES
INTERRUPT SOURCES
IEM CHANNEL
LEVEL/CHANNEL
SPI1
SPI1 end-transfer/overrun
0
RTI
COMP2 interrupt
1
RTI
COMP1 interrupt
2
RTI
TAP interrupt
3
SPI2
SPI2 end-transfer/overrun
4
GIO
GIO interrupt A
5
RESERVED
6
HET
HET interrupt 1
7
SPI4
SPI4 end-transfer/overrun
8
SCI1/SCI2
SCI1 or SCI2 error interrupt
9
SCI1
SCI1 receive interrupt
10
RESERVED
11
SPI5
SPI5 end-transfer/overrun
12
HECC1
HECC1 interrupt A
13
RESERVED
14
SPI3
SPI3 end-transfer/overrun
15
MibADC
MibADC end event conversion
16
SCI2
SCI2 receive interrupt
17
DMA
DMA interrupt 0
18
HECC3
HECC3 interrupt A
19
SCI1
SCI1 transmit interrupt
20
System
SW interrupt (SSI)
21
RESERVED
22
HET
HET interrupt 2
23
HECC1
HECC1 interrupt B
24
RESERVED
25
SCI2
SCI2 transmit interrupt
26
MibADC
MibADC end Group 1 conversion
27
DMA
DMA interrupt 1
28
GIO
GIO interrupt B
29
MibADC
MibADC end Group 2 conversion
30
HECC3
HECC3 interrupt B
31
Copyright 2005–2008, Texas Instruments Incorporated
17
Product Folder Link(s): TMS470R1B768
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