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FEATURES
www.ti.com ......................................................................................................................................................... SPNS108B – AUGUST 2005 – REVISED MAY 2008
16/32-Bit RISC Flash Microcontroller
Ten Communication Interfaces:
23
High-Performance Static CMOS Technology
–
Five Serial Peripheral Interfaces (SPIs)
TMS470R1x 16/32-Bit RISC Core (ARM7TDM)
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255 Programmable Baud Rates
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60-MHz (Pipeline Mode)
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Two Serial Communications Interfaces
(SCIs)
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Independent 16/32-Bit Instruction Set
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224 Selectable Baud Rates
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Open Architecture With Third-Party Support
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Asynchronous/Isosynchronous Modes
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Built-In Debug Module
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Three High-End CAN Controllers (HECCs)
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Utilizes Big-Endian Format
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32-Mailbox Capacity Each
Integrated Memory
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Fully Compliant With CAN Protocol,
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768K-Byte Program Flash
Version 2.0B
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3 Banks With 18 Contiguous Sectors
High-End Timer (HET)
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Internal State Machine for Programming
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32 Programmable I/O Channels:
and Erase
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24 High-Resolution Pins
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48K-Byte Static RAM (SRAM)
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8 Standard-Resolution Pins
15 Dedicated GIO Pins, 1 Input-Only GIO Pin,
and 71 Additional Peripheral I/Os
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High-Resolution Share Feature (XOR)
Operating Features
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High-End Timer RAM
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Core Supply Voltage (VCC): 1.81–2.05 V
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128-Instruction Capacity
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I/O Supply Voltage (VCCIO): 3.0–3.6 V
16-Channel 10-Bit Multi-Buffered ADC
(MibADC)
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Low-Power Modes: STANDBY and HALT
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256-Word FIFO Buffer
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Extended Industrial Temperature Range
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Single- or Continuous-Conversion Modes
470+ System Module
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1.55-s Minimum Sample and Conversion
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32-Bit Address Space Decoding
Time
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Bus Supervision for Memory and
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Calibration Mode and Self-Test Features
Peripherals
Eight External Interrupts
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Analog Watchdog (AWD) Timer
Flexible Interrupt Handling
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Real-Time Interrupt (RTI)
External Clock Prescale (ECP) Module
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System Integrity and Failure Detection
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Programmable Low-Frequency External
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Interrupt Expansion Module (IEM)
Clock (CLK)
Direct Memory Access (DMA) Controller
On-Chip Scan-Base Emulation Logic, IEEE
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32 Control Packets and 16 Channels
Standard 1149.1(1) (JTAG) Test-Access Port
Zero-Pin Phase-Locked Loop (ZPLL)-Based
144-Pin Plastic Low-Profile Quad Flatpack
Clock Module With Prescaler
(PGE Suffix)
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Multiply-by-4 or -8 Internal ZPLL Option
(1)
The test-access port is compatible with the IEEE Standard
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ZPLL Bypass Mode
1149.1-1990, IEEE Standard Test-Access Port and Boundary
Scan Architecture specification. Boundary scan is not
supported on this device.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
ARM7TDM is a trademark of Advanced RISC Machines Limited (ARM).
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All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 2005–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.