參數(shù)資料
型號： TMS470R1B768PGEQR
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144
封裝： PLASTIC, LQFP-144
文件頁數(shù)： 33/49頁
文件大?。?/td> 552K
代理商： TMS470R1B768PGEQR
SCIn ISOSYNCHRONOUS MODE TIMINGS INTERNAL CLOCK
Timing Requirements for Internal Clock SCIn Isosynchronous Mode
(1) (2) (3)
Data Valid
SCICLK
SCITX
SCIRX
tc(SCC)
tw(SCCL)
tw(SCCH)
td(SCCH TXV)
tv(TX)
tsu(RX SCCL)
tv(SCCL RX)
www.ti.com ......................................................................................................................................................... SPNS108B – AUGUST 2005 – REVISED MAY 2008
(BAUD + 1)
IS EVEN OR BAUD = 0
IS ODD AND BAUD
≠ 0
UNIT
MIN
MAX
MIN
MAX
Cycle time,
tc(SCC)
2tc(ICLK)
224 tc(ICLK)
3tc(ICLK)
(224 -1) tc(ICLK)
ns
SCInCLK
Pulse duration,
tw(SCCL)
0.5tc(SCC) – tf
0.5tc(SCC) + 5
0.5tc(SCC) + 0.5tc(ICLK) – tf
0.5tc(SCC) + 0.5tc(ICLK)
ns
SCInCLK low
Pulse duration,
tw(SCCH)
0.5tc(SCC) – tr
0.5tc(SCC) + 5
0.5tc(SCC) – 0.5tc(ICLK) – tr
0.5tc(SCC) – 0.5tc(ICLK)
ns
SCInCLK high
Delay time,
td(SCCH-TXV)
SCInCLK high to
10
ns
SCInTX valid
Valid time,
SCInTX data
tv(TX)
tc(SCC) – 10
ns
after SCInCLK
low
Setup time,
tsu(RX-SCCL)
SCInRX before
tc(ICLK) + tf + 20
ns
SCInCLK low
Valid time,
SCInRX data
tv(SCCL-RX)
–tc(ICLK) + tf + 20
ns
after SCInCLK
low
(1)
BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
(2)
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
(3)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
A.
Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK
falling edge.
Figure 16. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
Copyright 2005–2008, Texas Instruments Incorporated
39
Product Folder Link(s): TMS470R1B768
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