參數(shù)資料
型號(hào)： TMS470R1B768PGEQR
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144
封裝： PLASTIC, LQFP-144
文件頁數(shù)： 22/49頁
文件大?。?/td> 552K
代理商： TMS470R1B768PGEQR
ZPLL AND CLOCK SPECIFICATIONS
Timing Requirements for ZPLL Circuits Enabled or Disabled
Switching Characteristics over Recommended Operating Conditions for Clocks
(1) (2)
www.ti.com ......................................................................................................................................................... SPNS108B – AUGUST 2005 – REVISED MAY 2008
MIN
MAX
UNIT
f(OSC)
Input clock frequency
4
20
MHz
tc(OSC)
Cycle time, OSCIN
50
ns
tw(OSCIL)
Pulse duration, OSCIN low
15
ns
tw(OSCIH)
Pulse duration, OSCIN high
15
ns
f(OSCRST)
OSC FAIL frequency(1)
53
kHz
(1)
Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)
bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
PARAMETER
TEST CONDITIONS(3)
MIN
MAX
UNIT
Pipeline mode enabled
60
MHz
f(SYS)
System clock frequency(4)
Pipeline mode disabled
24
MHz
f(CONFIG)
System clock frequency
Flash config mode
24
MHz
Pipeline mode enabled
25
MHz
f(ICLK)
Interface clock frequency
Pipeline mode disabled
24
MHz
Pipeline mode enabled
25
MHz
f(ECLK)
External clock output frequency for ECP module
Pipeline mode disabled
24
MHz
Pipeline mode enabled
16.7
ns
tc(SYS)
Cycle time, system clock
Pipeline mode disabled
41.6
ns
tc(CONFIG)
Cycle time, system clock
Flash config mode
41.6
ns
Pipeline mode enabled
40
ns
tc(ICLK)
Cycle time, interface clock
Pipeline mode disabled
41.6
ns
Pipeline mode enabled
40
ns
tc(ECLK)
Cycle time, ECP module external clock output
Pipeline mode disabled
41.6
ns
(1)
When PLLDIS = 0, f(SYS) = M
f(OSC)/R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8}. R is the system-clock divider determined by the
CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit
(GLBCTRL.3).
When PLLDIS = 1, f(SYS) = f(OSC)/R, where R = {1,2,3,4,5,6,7,8}.
f(ICLK) = f(SYS)/X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1]
bits in the SYS module.
(2)
f(ECLK) = f(ICLK)/N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
(3)
Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
(4)
Flash Vread must be set to 5 V to achieve maximum system clock frequency.
Copyright 2005–2008, Texas Instruments Incorporated
29
Product Folder Link(s): TMS470R1B768
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