參數(shù)資料
型號(hào)： TMS470R1B768PGEQR
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144
封裝： PLASTIC, LQFP-144
文件頁(yè)數(shù)： 45/49頁(yè)
文件大?。?/td> 552K
代理商： TMS470R1B768PGEQR
Device Characteristics
www.ti.com ......................................................................................................................................................... SPNS108B – AUGUST 2005 – REVISED MAY 2008
Table 1 identifies all the characteristics of the TMS470R1B768 device except the SYSTEM and CPU, which are
generic.
Table 1. Device Characteristics
DEVICE DESCRIPTION
CHARACTERISTICS
COMMENTS For B768
TMS470R1B768
MEMORY
For the number of memory selects on this device, see Table 3, Memory Selection Assignment.
INTERNAL MEMORY
Pipeline/non-pipeline
Flash is pipeline-capable.
The B768 RAM is implemented in one 48K array selected by two
768K-byte flash
memory-select signals (see Table 3, Memory Selection Assignment).
48K-byte SRAM
PERIPHERALS
For the device-specific interrupt priority configurations, see Table 7, Interrupt Priority (IEM and CIM). And for the 1K peripheral address
ranges and their peripheral selects, see Table 5, B768 Peripherals, System Module, and Flash Base Addresses.
CLOCK
ZPLL
Zero-pin PLL has no external loop filter pins.
GENERAL-PURPOSE I/Os
15 I/O
Port A has eight (8) external pins, port B has one (1), port C has
three (3), and port D has four (4).
1 input only
ECP
YES
SCI
2 (3 pin)
SCI1 and SCI2
CAN (HECC and/or SCC)
3 HECCs
Three HECCs (HECC1, HECC2, and HECC3)
SPI (5-pin, 4-pin or 3-pin)
5 (5 pin)
SPI1, SPI2, SPI3, SPI4, and SPI5
The B768 device has both the logic and registers for a full 32-I/O
HET implemented and all 32 pins are available externally.
The high-resolution (HR) SHARE feature allows even HR pins to
share the next higher odd HR pin structures. This HR sharing is
HET with XOR Share
32 I/O
independent of whether or not the odd pin is available externally. If
an odd pin is available externally and shared, then the odd pin can
only be used as a general-purpose I/O. For more information on HR
SHARE, see the TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).
HET RAM
128-instruction capacity
The B768 device has both the logic and registers for a full
10-bit, 16-channel, 256-word
MibADC
16-channel MibADC implemented and all 16 pins are available
FIFO
externally.
CORE VOLTAGE
1.81V to 2.05 V
I/O VOLTAGE
3.0 V to 3.6 V
PINS
144
PACKAGE
PGE
Copyright 2005–2008, Texas Instruments Incorporated
5
Product Folder Link(s): TMS470R1B768
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