參數(shù)資料
型號(hào)： TMS470R1B768PGEQR
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144
封裝： PLASTIC, LQFP-144
文件頁數(shù)： 8/49頁
文件大?。?/td> 552K
代理商： TMS470R1B768PGEQR
Direct-Memory Access (DMA)
SPNS108B – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
The direct-memory access (DMA) controller transfers data to and from any specified location in the B768
memory map (except for restricted memory locations like the system control registers area). The DMA manages
up to 16 channels, and supports data transfer for both on-chip and off-chip memories and peripherals. The DMA
controller is connected to both the CPU and Peripheral busses, enabling these data transfers to occur in parallel
with CPU activity and thus maximizing overall system performance.
Although the DMA controller has two possible configurations, for the B768 device, the DMA controller
configuration is 32 control packets and 16 channels.
For the B768 DMA request hardwired configuration, see Table 6.
Table 6. DMA Request Lines Connections
MODULES
DMA REQUEST INTERRUPT SOURCES
DMA CHANNEL
RESERVED
DMAREQ[0]
SPI1
SPI1 end-receive
SPI1DMA0
DMAREQ[1]
SPI1
SPI1 end-transmit
SPI1DMA1
DMAREQ[2]
MibADC(1)
MibADC event
MibADCDMA0
DMAREQ[3]
MibADC(1)/SCI1
MibADC G1/SCI1 end-receive
MibADCDMA1/SCI1DMA0
DMAREQ[4]
MibADC(1)/SCI1
MibADC G2/SCI1 end-transmit
MibADCDMA2/SCI1DMA1
DMAREQ[5]
SPI4
SPI4 end-receive
SPI4DMA0
DMAREQ[6]
SPI2
SPI2 end-receive
SPI2DMA0
DMAREQ[7]
SPI2
SPI2 end-transmit
SPI2DMA1
DMAREQ[8]
RESERVED
DMAREQ[9]
RESERVED
DMAREQ[10]
SPI4
SPI4 end-transmit
SPI4DMA1
DMAREQ[11]
SPI5
SPI5 end-receive
SPI5DMA0
DMAREQ[12]
SPI5
SPI5 end-transmit
SPI5DMA1
DMAREQ[13]
SCI2/SPI3
SCI2 end-receive/SPI3 end-receive
SCI2DMA0/SPI3DMA0
DMAREQ[14]
SCI2/SPI3
SCI2 end-transmit/SPI3 end-transmit
SCI2DMA1/SPI3DMA1
DMAREQ[15]
(1)
The MibADC can be serviced by the DMA when the device is in buffered mode. For more information on buffered mode, see the
MibADC section of this data sheet and the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).
Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and generate
periodic interrupts so that the data can be read by the CPU. The control packets allow for the interrupt enable,
and the channels determine the priority level of the interrupt.
DMA transfers occur in one of two modes:
Non-request mode (used when transferring from memory to memory)
Request mode (used when transferring from memory to peripheral)
For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory Access
(DMA) Controller Reference Guide (literature number SPNU210).
16
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1B768
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