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| 型號： | TMS470R1B768PGEQR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 29/49頁 |
| 文件大?。?/td> | 552K |
| 代理商： | TMS470R1B768PGEQR |
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SPIn MASTER MODE TIMING PARAMETERS
SPIn Master Mode External Timing Parameters
SPInSOMI
SPInSIMO
SPInCLK
(clock polarity = 1)
SPInCLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
1
2
3
4
5
6
7
SPIn Master Mode External Timing Parameters
www.ti.com ......................................................................................................................................................... SPNS108B – AUGUST 2005 – REVISED MAY 2008
(CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)
(1) (2) (3) (see Figure 12)
NO.
MIN
MAX
UNIT
1
tc(SPC)M
Cycle time, SPInCLK(4)
100
256tc(ICLK)
ns
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
2(5)
ns
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
3(5)
ns
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
td(SPCH-SIMO)M
Delay time, SPInCLK high to SPInSIMO valid (clock polarity = 0)
10
4(5)
ns
td(SPCL-SIMO)M
Delay time, SPInCLK low to SPInSIMO valid (clock polarity = 1)
10
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0)
tc(SPC)M – 5 – tf
5(5)
ns
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1)
tc(SPC)M – 5 – tr
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low (clock polarity = 0)
6
6(5)
ns
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high (clock polarity = 1)
6
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0)
4
7(5)
ns
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1)
4
(1)
The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
(2)
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
(3)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(4)
When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥(PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
(5)
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 0)
(CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)
(1) (2) (3) (see Figure 13)
(1)
The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
(2)
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
(3)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
Copyright 2005–2008, Texas Instruments Incorporated
35
Product Folder Link(s): TMS470R1B768
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