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| 型號： | TMS470R1B768PGEQR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 2/49頁 |
| 文件大?。?/td> | 552K |
| 代理商： | TMS470R1B768PGEQR |
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SPNS108B – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
Table 2. Terminal Functions (continued)
TERMINAL
INTERNAL
TYPE(1)(2)
PULLUP/
DESCRIPTION
NAME
NO.
PULLDOWN(3)
SERIAL PERIPHERAL INTERFACE 5 (SPI5)
SPI5CLK
60
SPI5 clock. SPI5CLK can be programmed as a GIO pin.
SPI5ENA
61
SPI5 chip enable. SPI5ENA can be programmed as a GIO pin.
SPI5SCS
46
3.3-V I/O
IPD (20 A)
SPI5 slave chip select. SPI5SCS can be programmed as a GIO pin.
SPI5SIMO
58
SPI5 data stream. Slave in/master out. Can be programmed as a GIO pin.
SPI5SOMI
59
SPI5 data stream. Slave out/master in. Can be programmed as a GIO pin.
ZERO-PIN PHASE-LOCKED LOOP (ZPLL)
OSCIN
13
1.8-V I
Crystal connection pin or external clock input
OSCOUT
12
1.8-V O
External crystal connection pin
Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator
PLLDIS
73
3.3-V I
IPD (20 A)
becomes the system clock. If not in bypass mode, TI recommends that this
pin be connected to ground or pulled down to ground by an external resistor.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
SCI1CLK
89
3.3-V I/O
IPD (20 A)
SCI1 clock. SCI1CLK can be programmed as a GIO pin.
SCI1RX
91
3.3-V I/O
IPU (20 A)
SCI1 data receive. SCI1RX can be programmed as a GIO pin.
SCI1TX
90
3.3-V I/O
IPU (20 A)
SCI1 data transmit. SCI1TX can be programmed as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
SCI2CLK
45
3.3-V I/O
IPD (20 A)
SCI2 clock. SCI2CLK can be programmed as a GIO pin.
SCI2RX
43
3.3-V I/O
IPU (20 A)
SCI2 data receive. SCI2RX can be programmed as a GIO pin.
SCI2TX
44
3.3-V I/O
IPU (20 A)
SCI2 data transmit. SCI2TX can be programmed as a GIO pin.
SYSTEM MODULE (SYS)
Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output of
CLKOUT
83
3.3-V I/O
IPD (20 A)
SYSCLK, ICLK, or MCLK.
Input master chip power-up reset. External VCC monitor circuitry must assert a
PORRST
32
3.3-V I
IPD (20 A)
power-on reset.
Bidirectional reset. The internal circuitry can assert a reset, and an external
system reset can assert a device reset.
RST
15
3.3-V I/O
IPU (20 A)
On this pin, the output buffer is implemented as an open drain (drives low
only). To ensure an external reset is not arbitrarily generated, TI recommends
that an external pullup resistor be connected to this pin.
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
Analog watchdog reset. The AWD pin provides a system reset if the WD KEY
is not written in time by the system, providing an external RC network circuit
is connected. If the user is not using AWD, TI recommends that this pin be
connected to ground or pulled down to ground by an external resistor.
AWD
72
3.3-V I/O
IPD (20 A)
For more details on the external RC network circuit, see the TMS470R1x
System Module Reference Guide (literature number SPNU189) and the
application note Analog Watchdog Resistor, Capacitor and Discharge Interval
Selection Constraints (literature number SPNA005).
TEST/DEBUG (T/D)
TCK
76
3.3-V I
IPD (20 A)
Test clock. TCK controls the test hardware (JTAG).
Test data in. TDI inputs serial data to the test instruction register, test data
TDI
74
3.3-V I
IPU (20 A)
register, and programmable test address (JTAG).
Test data out. TDO outputs serial data from the test instruction register, test
TDO
75
3.3-V O
IPD (20 A)
data register, identification register, and programmable test address (JTAG).
10
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1B768
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