參數(shù)資料
型號: TMS320VC5409GGU-100
元件分類: 數(shù)字信號處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號處理器
文件頁數(shù): 63/78頁
文件大?。?/td> 1018K
代理商: TMS320VC5409GGU-100
TMS320VC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS082C – APRIL 1999 – REVISED MARCH 2000
63
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multichannel buffered serial port timing (continued)
timing requirements for McBSP as SPI master or slave: [H=0.5t
c(CO)
] CLKSTP = 10b, CLKXP = 0
(see Figure 33)
’5409-80, -100
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
tsu(BDRV-BCKXL)
th(BCKXL-BDRV)
tsu(BFXL-BCKXH)
tc(BCKX)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5t
c(CO)
] CLKSTP = 10b,
CLKXP = 0
(see Figure 33)
Setup time, BDR valid before BCLKX low
10
– 12H
ns
Hold time, BDR valid after BCLKX low
0
5 + 12H
ns
Setup time, BFSX low before BCLKX high
10
ns
Cycle time, BCLKX
12H
32H
ns
’5409-80, -100
PARAMETER
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
th(BCKXL-BFXL)
td(BFXL-BCKXH)
td(BCKXH-BDXV)
Hold time, BFSX low after BCLKX low§
Delay time, BFSX low to BCLKX high
T – 4
T + 4
ns
C – 5
C + 3
ns
Delay time, BCLKX high to BDX valid
– 3
7
6H + 5
10H + 14
ns
tdis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX low
C – 2
C + 3
ns
tdis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
2H+ 3
6H + 17
ns
td(BFXL-BDXV)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T =
BCLKX period = (1 + CLKGDV) * 2H
C =
BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
§FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
Delay time, BFSX low to BDX valid
4H + 2
8H + 17
ns
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
BCLKX
BFSX
BDX
BDR
tsu(BDRV-BCLXL)
td(BCKXH-BDXV)
th(BCKXL-BDRV)
tdis(BFXH-BDXHZ)
tdis(BCKXL-BDXHZ)
th(BCKXL-BFXL)
td(BFXL-BDXV)
td(BFXL-BCKXH)
LSB
MSB
tsu(BFXL-BCKXH)
tc(BCKX)
Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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