參數(shù)資料
型號： TMS320VC5409GGU-100
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 60/78頁
文件大?。?/td> 1018K
代理商： TMS320VC5409GGU-100
TMS320VC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS082C – APRIL 1999 – REVISED MARCH 2000
60
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multichannel buffered serial port timing (continued)
switching characteristics for the McBSP
[H=0.5t
c(CO)
] (see Figure 30 and Figure 31)
PARAMETER
MIN
MAX
UNIT
tc(BCKRX)
tw(BCKRXH)
tw(BCKRXL)
td(BCKRH-BFRV)
Cycle time, BCLKR/X
BCLKR/X int
4H
ns
Pulse duration, BCLKR/X high
BCLKR/X int
D–3
C–3
D+1
C+1
ns
Pulse duration, BCLKR/X low
BCLKR/X int
ns
Delay time, BCLKR high to internal BFSR valid
BCLKR int
–2
2
ns
td(BCKXH-BFXV)
Delay time BCLKX high to internal BFSX valid
Delay time, BCLKX high to internal BFSX valid
BCLKX int
0
6
ns
BCLKX ext
4
12
tdis(BCKXH-BDXHZ)
Disable time BCLKX high to BDX high impedance following last data bit
Disable time, BCLKX high to BDX high impedance following last data bit
BCLKX int
–4
7
ns
BCLKX ext
3
9
Delay time, BCLKX high to BDX valid. This applies to all bits except the first
bit transmitted.
BCLKX int
0
7
lies to all bits exce t the first
BCLKX ext
4
12
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid.§
Only applies to first bit transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b) modes
Enable time, BCLKX high to BDX driven.§
Only applies to first bit transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b) modes
Delay time, BFSX high to BDX valid.§
Only applies to first bit transmitted when in Data Delay 0
(XDATDLY=00b) mode.
Enable time, BFSX high to BDX driven.§
Only applies to first bit transmitted when in Data Delay 0
(XDATDLY=00b) mode
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of
that signal are
also inverted.
T=BCLKRX period = (1 + CLKGDV) * 2H
C=BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D=BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§See the TMS320C54x Enhanced Peripherals Reference Set, Volume 5(literature number SPRU302) for a description of the DX enable (DXENA)
and data delay features of the McBSP.
The transmit delay enable (DXENA) and A-bis mode (ABIS) features of the McBSP are not implemented on the TMS320VC5409.
DXENA = 0
BCLKX int
7
ns
BCLKX ext
12
te(BCKXH-BDX)
DXENA = 0
BCLKX int
–4
ns
BCLKX ext
2
td(BFXH-BDXV)
DXENA = 0
BFSX int
2
ns
BFSX ext
12
te(BFXH-BDX)
DXENA = 0
BFSX int
–1
ns
BFSX ext
2
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參數(shù)描述
TMS320VC5409GGU-80 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320VC5409PGE100 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Sig Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320VC5409PGE100 制造商:Texas Instruments 功能描述:Digital Signal Processor IC
TMS320VC5409PGE-80 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320VC5409ZGU100 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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