參數(shù)資料
型號： TMS320VC5409GGU-100
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 21/78頁
文件大小： 1018K
代理商： TMS320VC5409GGU-100
TMS320VC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS082C – APRIL 1999 – REVISED MARCH 2000
21
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multichannel buffered serial ports (McBSPs) (continued)
Table 6. Pin Control Register (PCR) Bit Field Description
BIT
NAME
FUNCTION
15 – 14
Reserved
Reserved. Pins are not used.
13
XIOEN
Transmit/Receive general-purpose I/O mode ONLY when XRST=0 in the SPCR(1/2)
XIOEN = 0
XIOEN = 1
DX pin is not a general-purpose output. FSX and CLKX are not general-purpose I/Os.
DX pin is a general-purpose output. FSX and CLKX are general-purpose I/Os. These serial port
pins do not perform serial port operations.
12
RIOEN
Transmit/Receive general-purpose I/O mode ONLY when RRST=0 in the SPCR(1/2)
RIOEN = 0
DR and CLKS pins are not general-purpose inputs. FSR and CLKR are not general-purpose
I/Os.
DR and CLKS pins are general-purpose inputs. FSR and CLKR are general-purpose I/Os.
These serial port pins do not perform serial port operations. The CLKS pin is affected by a
combination of RRST and RIOEN signals of the receiver.
RIOEN = 1
11
FSXM
Transmit frame synchronization mode
FSRM = 0
FSRM = 1
Frame synchronization signal derived from an external source.
Frame synchronization is determined by the sample rate generator frame synchronization mode
bit (FSGM) in the SRGR2.
10
FSRM
Receive frame synchronization mode
FSRM = 0
FSRM = 1
Frame synchronization pulses generated by an external device. FSR is an input pin.
Frame synchronization generated internally by the sample rate generator. FSR is an output pin
except when GSYNC=1 in the SRGR.
9
CLKRM
Receiver clock mode
Case 1: Digital loop-back mode is not set (DLB=0) in SPCR1.
CLKRM = 0
CLKRM= 1
Receive clock (CLKR) is an input pin driven by an external clock.
CLKR is an output pin and is driven by the internal sample rate generator
Case 2: Digital loop-back mode set (DLB=1) in SPCR1
CLKRM = 0
Receive clock (Notthe CLKR pin) is driven by transmit clock (CLKX), which is based on CLKXM
bit in the PCR. CLKR pin is in high-impedance mode.
CLKR is an output pin and is driven by the transmit clock. The transmit clock is derived based
on the CLKXM bit in the PCR.
CLKRM= 1
8
CLKXM
Transmitter clock mode
CLKXM = 0
CLKXM= 1
Receiver/transmitter clock is driven by an external clock with CLK(R/X) as an input pin
CLK(R/X) is an output pin and is driven by the internal sample rate generator
During SPI mode (CLKSTP is a non-zero value):
CLKXM = 0
McBSP is a slave and clock (CLKX) is driven by the SPI master in the system. CLKR is
internally driven by CLKX.
McBSP is a master and generates the clock (CLKX) to drive its receive clock (CLKR) and the
shift clock of the SPI-compliant slaves in the system.
CLKXM= 1
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TMS320VC5409PGE100 制造商:Texas Instruments 功能描述:Digital Signal Processor IC
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