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參數(shù)資料
| 型號： | TMS320UVC5409 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 7/60頁 |
| 文件大?。?/td> | 772K |
| 代理商： | TMS320UVC5409 |
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TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
NAME
DESCRIPTION
TYPE
TERMINAL
CLOCK/TIMER SIGNALS (CONTINUED)
CLKMD1
CLKMD2
CLKMD3
I
Clock mode-select signals. These inputs select the mode that the clock generator is initialized to after reset. The
logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized
to the selected mode. After reset, the clock mode can be changed through software, but the clock mode-select
signals have no effect until the device is reset again.
X2/CLKIN
I
Clock input. An external clock source should be provided at this input. The frequency of this clock source can
be internally divided to produce the CPU clock.
X1
O
This pin is reserved and should be left unconnected.
TOUT0
O/Z
Timer0 output. TOUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT
cycle wide. TOUT0 also goes into the high-impedance state when EMU1/OFF is low.
TOUT1
O/Z
Timer1 output. TOUT1 signals a pulse when the on-chip timer1 counts down past zero. The pulse is one
CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT pin of the HPI and is only available when
the HPI is disabled. TOUT1 also goes into the high-impedance state when EMU1/OFF is low.
MULTICHANNEL BUFFERED SERIAL PORT SIGNALS
BCLKR0
BCLKR1
I/O/Z
Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.
BDR0
BDR1
I
Serial data receive input
BFSR0
BFSR1
I/O/Z
Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.
BCLKX0
BCLKX1
I/O/Z
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when
EMU1/OFF goes low.
BDX0
BDX1
O/Z
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted, or when EMU1/OFF is low.
BFSX0
BFSX1
I/O/Z
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX
can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the
high-impedance state when EMU1/OFF is low.
MISCELLANEOUS SIGNAL
NC
No connection
HOST-PORT INTERFACE SIGNALS
HD0–HD7
I/O/Z
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the
HPI registers. These pins can also be used as general-purpose I/O pins. HD0–HD7 is placed in the
high-impedance state when not outputting data or when EMU1/OFF is low. The HPI data bus includes bus
holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not
being driven by the ’UVC5402, the bus holders keep the pins at the previous logic level. The HPI data bus holders
are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR.
HCNTL0
HCNTL1
I
Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have
internal pullup resistors that are only enabled when HPIENA = 0.
HBIL
I
Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup
resistor that is only enabled when HPIENA = 0.
HCS
I
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input
has an internal pullup resistor that is only enabled when HPIENA = 0.
HDS1
HDS2
I
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs
have internal pullup resistors that are only enabled when HPIENA = 0.
HAS
I
Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA
register. HAS has an internal pullup resistor that is only enabled when HPIENA = 0.
I = input, O = output, Z = high impedance, S = supply
P
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