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| 型號(hào)： | TMS320UVC5409 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 23/60頁(yè) |
| 文件大?。?/td> | 772K |
| 代理商： | TMS320UVC5409 |
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TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
23
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
memory-mapped registers (continued)
Table 10. Peripheral Memory-Mapped Registers
NAME
ADDRESS
DESCRIPTION
TYPE
DRR20
20h
áááááááááááááááááá
McBSP0 data receive register 2
McBSP #0
DRR10
21h
áááááááááááááááááá
McBSP0 data transmit register 2
McBSP0 data receive register 1
McBSP #0
DXR20
22h
áááááááááááááááááá
áááááááááááááááááá
McBSP #0
DXR10
23h
McBSP #0
TIM
24h
áááááááááááááááááá
Timer0
PRD
25h
áááááááááááááááááá
Timer0
TCR
26h
áááááááááááááááááá
Timer0 control register
Timer0
–
27h
SWWSR
28h
áááááááááááááááááá
Reserved
Software wait-state register
External Bus
BSCR
29h
áááááááááááááááááá
áááááááááááááááááá
áááááááááááááááááá
Bank-switching control register
External Bus
–
2Ah
SWCR
2Bh
Software wait-state control register
External Bus
HPIC
2Ch
áááááááááááááááááá
HPI
–
2Dh–2Fh
TIM1
30h
áááááááááááááááááá
Reserved
áááááááááááááááááááááááááá
Timer1
PRD1
31h
áááááááááááááááááá
Timer1 period counter
Timer1
TCR1
áááááááááááááááááááááááááááááá
SPSD0
32h
áááááááááááááááááá
Timer1 control register
38h
McBSP0 subbank data register
Timer1
–
33h–37h
SPSA0
áááááá
McBSP #0
áááááááááááááááááááááááááááááá
39h
McBSP #0
áááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááá
DRR21
40h
áááááááááááááááááá
áááááááááááááááááá
Reserved
McBSP #1
DRR11
41h
áááááááááááááááááá
McBSP1 data receive register 1
McBSP1 data transmit register 1
McBSP #1
DXR21
42h
McBSP1 data transmit register 2
McBSP #1
DXR11
43h
áááááááááááááááááá
McBSP #1
–
44h–47h
áááááááááááááááááá
áááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááá
DMPREC
54h
áááááááááááááááááá
áááááááááááááááááááááááááá
–
59h–5Fh
Reserved
See Table 11 for a detailed description of the McBSP control registers and their subaddresses.
See Table 12 for a detailed description of the DMA subbank addressed registers.
56h
DMA
DMSA
áááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááá
CLKMD
55h
áááááááááááááááááá
58h
DMA
DMSDI
DMA subbank data register with autoincrement
DMA subbank data register
áááááá
DMA
DMSDN
57h
PLL
DMA
P
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