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TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
51
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multichannel buffered serial port timing (continued)
timing requirements for McBSP as SPI master or slave: [H=0.5t
c(CO)
] CLKSTP = 11b, CLKXP = 0
(see Figure 28)
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
tsu(BDRV-BCKXH)
th(BCKXH-BDRV)
tsu(BFXL-BCKXH)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Setup time, BDR valid before BCLKX high
15
–12H
ns
Hold time, BDR valid after BCLKX high
6
5+12H
ns
Setup time, BFSX low before BCLKX high
15
ns
switching characteristics for McBSP as SPI master or slave: [H=0.5t
c(CO)
] CLKSTP = 11b,
CLKXP = 0
(see Figure 28)
PARAMETER
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
th(BCKXL-BFXL)
td(BFXL-BCKXH)
td(BCKXL-BDXV)
Hold time, BFSX low after BCLKX low§
Delay time, BFSX low to BCLKX high
C–2
C+3
ns
T–2
T+3
ns
Delay time, BCLKX low to BDX valid
0
6
6H+10
10H+25
ns
tdis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX low
0
6
6H+10
10H+25
ns
td(BFXL-BDXV)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T =
BCLKX period = (1 + CLKGDV) * 2H
C =
BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D =
BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
Delay time, BFSX low to BDX valid
D–2
D+4
4H+10
8H+25
ns
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
BCLKX
BFSX
BDX
BDR
td(BFXL-BCKXH)
tdis(BCKXL-BDXHZ)
td(BCKXL-BDXV)
th(BCKXH-BDRV)
tsu(BDRV-BCKXH)
td(BFXL-BDXV)
th(BCKXL-BFXL)
LSB
MSB
tsu(BFXL-BCKXH)
Figure 28. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
P