參數(shù)資料
型號(hào)： TMS320UVC5409
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號(hào)處理器
文件頁數(shù)： 21/60頁
文件大?。?/td> 772K
代理商： TMS320UVC5409
TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
21
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
DMA controller synchronization events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit
field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization event
for a channel. The list of possible events and the DSYN values are shown in Table 7.
Table 7. DMA Synchronization Events
DSYN VALUE
DMA SYNCHRONIZATION EVENT
0000b
No synchronization used
0001b
McBSP0 receive event
0010b
McBSP0 transmit event
0011–0100b
Reserved
0101b
McBSP1 receive event
0110b
McBSP1 transmit event
0111b–0110b
Reserved
1101b
Timer0 interrupt
1110b
External interrupt 3
1111b
Timer1 interrupt
DMA channel interrupt selection
The DMA controller can generate a CPU interrupt for each of the six channels. However, channels 1, 2,
and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an interrupt line with the receive
and transmit portions of McBSP1 (IMR/IFR bits 10 and 11), and DMA channel 1 shares an interrupt line with
timer 1 (IMR/IFR bit 7). When the ’UVC5402 is reset, the interrupts from these three DMA channels are
deselected. The INTSEL bit field in the DMA channel priority and enable control (DMPREC) register can be used
to select these interrupts, as shown in Table 8.
Table 8. DMA Channel Interrupt Selection
INTSEL Value
IMR/IFR[7]
IMR/IFR[10]
IMR/IFR[11]
00b (reset)
TINT1
BRINT1
BXINT1
01b
TINT1
DMAC2
DMAC3
10b
DMAC1
DMAC2
DMAC3
11b
Reserved
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