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參數(shù)資料
| 型號： | TMS320UVC5409 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 31/60頁 |
| 文件大?。?/td> | 772K |
| 代理商： | TMS320UVC5409 |
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TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
divide-by-two clock option
The frequency of the external reference clock provided at the X2/CLKIN pin can be divided by a factor of two
to generate the internal machine cycle. The selection of the clock mode is described in the clock generator
section.
The external frequency injected must conform to specifications listed in the timing requirements table.
switching characteristics over recommended operating conditions [H = 0.5t
c(CO)
]
(see Figure 8
and the recommended operating conditions table)
PARAMETER
MIN
TYP
MAX
UNIT
tc(CO)
td(CIH-CO)
tf(CO)
tr(CO)
tw(COL)
tw(COH)
This device utilizes a fully static design and therefore can operate with tc(CI) approaching
∞
. The device is characterized at frequencies
approaching 0 Hz.
It is recommended that the PLL clocking option be used for maximum frequency operation.
Cycle time, CLKOUT
33
ns
Delay time, X2/CLKIN high to CLKOUT high/low
15
25
ns
Fall time, CLKOUT
5
ns
Rise time, CLKOUT
5
ns
Pulse duration, CLKOUT low
H–4
H–2
ns
Pulse duration, CLKOUT high
H–4
H–2
ns
timing requirements (see Figure 8)
MIN
MAX
UNIT
tc(CI)
tf(CI)
tr(CI)
This device utilizes a fully static design and therefore can operate with tc(CI) approaching
∞
. The device is characterized at frequencies
approaching 0 Hz.
Cycle time, X2/CLKIN
15
ns
Fall time, X2/CLKIN
8
ns
Rise time, X2/CLKIN
8
ns
tr(CO)
tf(CO)
CLKOUT
X2/CLKIN
tw(COL)
td(CIH-CO)
tf(CI)
tr(CI)
tc(CO)
tc(CI)
tw(COH)
Figure 8. External Divide-by-Two Clock Timing
P
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