參數(shù)資料
型號(hào)： TMS320UVC5409
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 37/60頁(yè)
文件大?。?/td> 772K
代理商： TMS320UVC5409
TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
37
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a parallel I/O port write
(IOSTRB = 0)[H = 0.5 t
c(CO)
]
(see Figure 12)
PARAMETER
MIN
MAX
UNIT
td(CLKL-A)
td(CLKH-ISTRBL)
td(CLKH-D)IOW
td(CLKH-ISTRBH)
td(CLKL-RWL)
td(CLKL-RWH)
th(A)IOW
th(D)IOW
tsu(D)IOSTRBH
tsu(A)IOSTRBL
Address and IS timings are included in timings referenced as address.
Delay time, CLKOUT low to address valid
0
8
ns
Delay time, CLKOUT high to IOSTRB low
0
8
ns
Delay time, CLKOUT high to write data valid
H–5
H+3
ns
Delay time, CLKOUT high to IOSTRB high
0
8
ns
Delay time, CLKOUT low to R/W low
0
8
ns
Delay time, CLKOUT low to R/W high
0
8
ns
Hold time, address valid after CLKOUT low
0
8
ns
Hold time, write data after IOSTRB high
H–3
H+3
ns
Setup time, write data before IOSTRB high
H–3
H+1
ns
Setup time, address valid before IOSTRB low
H–3
H+3
ns
IS
R/W
IOSTRB
D[15:0]
A[19:0]
CLKOUT
td(CLKH-ISTRBH)
th(A)IOW
th(D)IOW
td(CLKH-D)IOW
td(CLKH-ISTRBL)
td(CLKL-A)
td(CLKL-RWL)
td(CLKL-RWH)
tsu(A)IOSTRBL
tsu(D)IOSTRBH
Figure 12. Parallel I/O Port Write (IOSTRB = 0)
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