參數(shù)資料
型號(hào)： TMS320UVC5409
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 36/60頁(yè)
文件大?。?/td> 772K
代理商： TMS320UVC5409
TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
36
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a parallel I/O port read
(IOSTRB = 0)
(see Figure 11)
PARAMETER
MIN
MAX
UNIT
td(CLKL-A)
td(CLKH-ISTRBL)
td(CLKH-ISTRBH)
th(A)IOR
Address and IS timings are included in timings referenced as address.
Delay time, CLKOUT low to address valid
0
8
ns
Delay time, CLKOUT high to IOSTRB low
0
8
ns
Delay time, CLKOUT high to IOSTRB high
0
8
ns
Hold time, address after CLKOUT low
0
8
ns
timing requirements for a parallel I/O port read (IOSTRB = 0)[H = 0.5 t
c(CO)
]
(see Figure 11)
MIN
MAX
UNIT
ta(A)IO
ta(ISTRBL)IO
tsu(D)IOR
th(D)IOR
th(ISTRBH-D)R
Address and IS timings are included in timings referenced as address.
Access time, read data access from address valid
3H–15
ns
Access time, read data access from IOSTRB low
2H–15
ns
Setup time, read data before CLKOUT high
10
ns
Hold time, read data after CLKOUT high
0
ns
Hold time, read data after IOSTRB high
0
ns
IS
R/W
IOSTRB
D[15:0]
A[19:0]
CLKOUT
th(A)IOR
td(CLKH-ISTRBH)
th(D)IOR
tsu(D)IOR
ta(A)IO
td(CLKH-ISTRBL)
td(CLKL-A)
ta(ISTRBL)IO
th(ISTRBH-D)R
Figure 11. Parallel I/O Port Read (IOSTRB = 0)
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