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參數(shù)資料
| 型號： | TMS320UVC5409 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 32/60頁 |
| 文件大?。?/td> | 772K |
| 代理商： | TMS320UVC5409 |
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TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
32
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
memory and parallel I/O interface timing
switching characteristics over recommended operating conditions for a memory read
(MSTRB = 0)
(see Figure 9)
PARAMETER
MIN
MAX
UNIT
td(CLKL-A)
td(CLKH-A)
td(CLKL-MSL)
td(CLKL-MSH)
th(CLKL-A)R
th(CLKH-A)R
Address, PS, and DS timings are all included in timings referenced as address.
In the case of a memory read preceded by a memory read
§In the case of a memory read preceded by a memory write
Delay time, CLKOUT low to address valid
Delay time, CLKOUT high (transition) to address valid§
0
8
ns
0
8
ns
Delay time, CLKOUT low to MSTRB low
0
8
ns
Delay time, CLKOUT low to MSTRB high
Hold time, address valid after CLKOUT low
Hold time, address valid after CLKOUT high§
0
8
ns
0
8
ns
0
8
ns
timing requirements for a memory read (MSTRB = 0) [H = 0.5 t
c(CO)
]
(see Figure 9)
MIN
MAX
UNIT
ta(A)M
ta(MSTRBL)
tsu(D)R
th(D)R
th(A-D)R
th(D)MSTRBH
Address, PS, and DS timings are all included in timings referenced as address.
Access time, read data access from address valid
2H–15
ns
Access time, read data access from MSTRB low
2H–15
ns
Setup time, read data before CLKOUT low
10
ns
Hold time, read data after CLKOUT low
0
ns
Hold time, read data after address invalid
0
ns
Hold time, read data after MSTRB high
0
ns
P
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