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參數(shù)資料
| 型號： | TMS320UVC5409 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 43/60頁 |
| 文件大?。?/td> | 772K |
| 代理商： | TMS320UVC5409 |
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TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
reset, BIO, interrupt, and
MP/MC timings
timing requirements for reset, BIO, interrupt, and MP/MC
[H = 0.5 t
c(CO)
]
(see Figure 18, Figure 19,
and Figure 20)
MIN
MAX
UNIT
ns
th(RS)
th(BIO)
th(INT)
th(MPMC)
tw(RSL)
tw(BIO)S
tw(BIO)A
tw(INTH)S
tw(INTH)A
tw(INTL)S
tw(INTL)A
tw(INTL)WKP
tsu(RS)
tsu(BIO)
tsu(INT)
tsu(MPMC)
The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is
corresponding to three CLKOUT sampling sequences.
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50
μ
s to ensure
synchronization and lock-in of the PLL.
§Note that RS may cause a change in clock frequency, therefore changing the value of H.
Divide-by-two mode
Hold time, RS after CLKOUT low
0
Hold time, BIO after CLKOUT low
Hold time, INTn, NMI, after CLKOUT low
0
ns
0
ns
Hold time, MP/MC after CLKOUT low
Pulse duration, RS low§
0
ns
4H+5
ns
Pulse duration, BIO low, synchronous
2H+5
ns
Pulse duration, BIO low, asynchronous
4H
ns
Pulse duration, INTn, NMI high (synchronous)
2H+7
ns
Pulse duration, INTn, NMI high (asynchronous)
4H
ns
Pulse duration, INTn, NMI low (synchronous)
2H+7
ns
Pulse duration, INTn, NMI low (asynchronous)
4H
ns
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
Setup time, RS before X2/CLKIN low
12
ns
5
ns
Setup time, BIO before CLKOUT low
12
15
ns
Setup time, INTn, NMI, RS before CLKOUT low
12
15
ns
Setup time, MP/MC before CLKOUT low
12
ns
P
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