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參數資料
| 型號： | TMS320UVC5409 |
| 元件分類： | 數字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數字信號處理器 |
| 文件頁數： | 27/60頁 |
| 文件大?。?/td> | 772K |
| 代理商： | TMS320UVC5409 |
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TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
27
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupts (continued)
The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in Figure 7.
15–14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RES
DMAC5
DMAC4
BXINT1
or
DMAC3
BRINT1
or
DMAC2
HPINT
INT3
TINT1
or
DMAC1
DMAC0
BXINT0
BRINT0
TINT0
INT2
INT1
INT0
Figure 7. IFR and IMR Registers
Table 14. IFR and IMR Register Bit Fields
BIT
FUNCTION
NUMBER
NAME
15–14
–
Reserved for future expansion
13
DMAC5
DMA channel 5 interrupt flag/mask bit
12
DMAC4
DMA channel 4 interrupt flag/mask bit
11
BXINT1/DMAC3
This bit can be configured as either the McBSP1 transmit interrupt flag/mask bit, or the DMA
channel 3 interrupt flag/mask bit. The selection is made in the DMPREC register.
10
BRINT1/DMAC2
This bit can be configured as either the McBSP1 receive interrupt flag/mask bit, or the DMA
channel 2 interrupt flag/mask bit. The selection is made in the DMPREC register.
9
HPINT
Host to ’54x interrupt flag/mask
8
INT3
External interrupt 3 flag/mask
7
TINT1/DMAC1
This bit can be configured as either the timer1 interrupt flag/mask bit, or the DMA channel 1
interrupt flag/mask bit. The selection is made in the DMPREC register.
6
DMAC0
DMA channel 0 interrupt flag/mask bit
5
BXINT0
McBSP0 transmit interrupt flag/mask bit
4
BRINT0
McBSP0 receive interrupt flag/mask bit
3
TINT0
Timer 0 interrupt flag/mask bit
2
INT2
External interrupt 2 flag/mask bit
1
INT1
External interrupt 1 flag/mask bit
0
INT0
External interrupt 0 flag/mask bit
P
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