參數(shù)資料
型號： TMS320LC57S
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(35/50ns指令周期，并行邏輯單元，可編程PLL，全雙工同步串行口的DSP)
中文描述： 數(shù)字信號處理器（35/50ns指令周期，并行邏輯單元，可編程鎖相環(huán)，全雙工同步串行口的數(shù)字信號處理器）
文件頁數(shù)： 77/87頁
文件大?。?/td> 1864K
代理商： TMS320LC57S
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
77
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
HOST PORT INTERFACE (TMS320C57S, TMS320LC57 ONLY)
switching characteristics over recommended operating conditions [H = 0.5t
c(CO)
] (See Notes 11
and 12) (see Figure 30 through Figure 33)
PARAMETER
MIN
MAX
UNIT
td(DSL-HDV)
Delay time, DS low to HD valid
5
ns
td(HEL-HDV1)
Delay time, HDS falling to HD valid for first byte of a subsequent read:
Case 1: Shared-access mode if tw(HDS)h < 7H
Case 2: Shared-access mode if tw(HDS)h > 7H
Case 3: Host-only mode if tw(HDS)h < 7H
Case 4: Host-only mode if tw(HDS)h > 7H
Delay time, DS low to HD valid, second byte
7H+20–tw(DSH)
20
40–tw(DSH)
20
ns
td(DSL-HDV2)
td(DSH-HYH)
tsu(HDV-HYH)
th(DSH-HDV)
td(COH-HYH)
td(DSH-HYL)
td(COH-HTX)
Host-only mode timings apply for read accesses to HPIC or HPIA, write accesses to BOB, and resetting DSPINT or HINT to 0 in shared-access
mode. HRDY does not go low for these accesses.
Shared-access mode timings are met automatically if HRDY is used.
§HD release
NOTES: 11. SAM = shared-access mode, HOM = host-only mode
HAD stands for HCNTRL0, HCNTRL1, and HR/W.
HDS refers to either HDS1 or HDS2.
DS refers to the logical OR of HCS and HDS.
12. On host-read accesses to the HPI, the setup time of HD before DS rising edge depends on the host waveforms and cannot be
specified here.
20
ns
Delay time, DS high to HRDY high
ns
Setup time, HD valid before HRDY rising edge
3H–10
ns
Hold time, HD valid after DS rising edge
0
12§
ns
Delay time, CLKOUT rising edge to HRDY high
10
ns
Delay time, HDS or HCS high to HRDY low
12
ns
Delay time, CLKOUT rising edge to HINT change
10
ns
timing requirements over recommended operating conditions [H = 0.5t
c(CO)
] (See Note 11)
(see Figure 30 through Figure 33)
MIN
MAX
UNIT
tsu(HBV-DSL)
th(DSL-HBV)
tsu(HSL-DSL)
tw(DSL)
tw(DSH)
Setup time, HAD/HBIL valid before HAS or DS falling edge#
Hold time, HAD/HBIL valid after HAS or DS falling edge#
10
ns
10
ns
Setup time, HAS low before DS falling edge
10
ns
Pulse duration, DS low
25
ns
Pulse duration, DS high
10
ns
tc(DSH-DSH)
Cycle time, DS rising edge to next DS rising edge:
Case 1: When using HRDY (see Figure 32)
Case 2a: SAM accesses and HOM active writes to DSPINT or HINT without using HRDY
(see Figure 30 and Figure 31)
Case 2b: When not using HRDY for other HOM accesses
50
10H
50
ns
tsu(HDV-DSH)
th(DSH-HDV)
A host not using HRDY must meet the 10 H requirement all the time unless a software handshake is used to change the access rate according
to the HPI mode.
#When HAS is tied to VDD, timing is referenced to DS.
NOTE 11: SAM = shared-access mode, HOM = host-only mode
HAD stands for HCNTRL0, HCNTRL1, and HR/W.
HDS refers to either HDS1 or HDS2.
DS refers to the logical OR of HCS and HDS.
Setup time, HD valid before DS rising edge
10
ns
Hold time, HD valid after DS rising edge
0
ns
相關(guān)PDF資料
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TMS320UVC5409 Fixed-Point Digital Signal Processor(定點(diǎn)DSP)
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