參數(shù)資料
型號: TMS320LC57S
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors(35/50ns指令周期,并行邏輯單元,可編程PLL,全雙工同步串行口的DSP)
中文描述: 數(shù)字信號處理器(35/50ns指令周期,并行邏輯單元,可編程鎖相環(huán),全雙工同步串行口的數(shù)字信號處理器)
文件頁數(shù): 75/87頁
文件大?。?/td> 1864K
代理商: TMS320LC57S
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
75
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
BUFFERED SERIAL-PORT TRANSMIT TIMING OF EXTERNAL FRAMES (SEE NOTES 9 AND 10)
switching characteristics over recommended operating conditions (see Figure 28)
PARAMETER
MIN
MAX
UNIT
td(CXH-DXV)
tdis(CXH-DX)
tdis(CXH-DX)PCM
ten(CXH-DX)PCM
th(CXH-DXV)
Delay time, DX valid after CLKX rising edge
5
21
ns
Disable time, DX invalid after CLKX rising edge
5
15
ns
Disable time in PCM mode, DX invalid after CLKX rising edge
15
ns
Enable time in PCM mode, DX valid after CLKX rising edge
21
ns
Hold time, DX valid after CLKX rising edge
5
20
ns
timing requirements over recommended operating conditions (see Figure 28)
MIN
MAX
UNIT
tc(SCK)
tf(SCK)
tr(SCK)
tw(SCK)
tsu(FX-CXL)
th(CXL-FX)
The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching
. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
Values derived from characterization data and not tested
§If the FSX pulse does not meet this specification, the first bit of the serial data is driven on the DX pin until FSX goes low (sampled on falling edge
of CLKX). After falling edge of the FSX, data is shifted out on the DX pin.
NOTE 9: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on
the source of FSX, and CLKX timings always are dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX. External FSX timings are obtained from the “timing requirements over recommended operating
conditions” table listed in the “Buffered Serial-Port Transmit Timing of External Frames” section and internal FSX timings are obtained
from the “switching characteristics over recommended operating conditions” table listed under the “Buffered Serial-Port Transmit Timing
of Internal Frame and Internal Clock” section. Internal CLKX timings are obtained from the “switching characteristics over recommended
operating conditions” table listed under the “Buffered Serial-Port Transmit Timing of Internal Frame and Internal Clock” section and
external CLKX timings are obtained from the “timing requirements over recommended operating conditions” table in the “Buffered
Serial-Port Transmit Timing of External Frames” section.
NOTE 10: Timings for CLKX and FSX are given with polarity bits (CLKP and FSP) set to 0
Cycle time, serial-port clock
25
ns
Fall time, serial-port clock
4
4
ns
Rise time, serial-port clock
ns
Pulse duration, serial-port clock low/high
8.5
ns
Setup time, FSX before CLKX falling edge
5
ns
Hold time, FSX after CLKX falling edge
5
tc(SCK)–5§
ns
DX BIt
FSX
CLKX
8/16
7/15
2
1
th(CXH-DXV)
td(CXH-DXV)
tw(SCK)
tr(SCK)
tf(SCK)
tw(SCK)
tc(SCK)
th(CXL-FX)
tdis(CXH-DX)
tsu(FX-CXL)
Figure 28. Buffered Serial-Port Transmit Timing of External Clocks and External Frames
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