參數(shù)資料
型號(hào)： TMS320LC57S
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(35/50ns指令周期，并行邏輯單元，可編程PLL，全雙工同步串行口的DSP)
中文描述： 數(shù)字信號(hào)處理器（35/50ns指令周期，并行邏輯單元，可編程鎖相環(huán)，全雙工同步串行口的數(shù)字信號(hào)處理器）
文件頁(yè)數(shù)： 37/87頁(yè)
文件大?。?/td> 1864K
代理商： TMS320LC57S
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
37
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
instruction set summary (continued)
Table 6. Opcode Symbols
SYMBOL
DESCRIPTION
A
Address
ACC
Accumulator
ACCB
Accumulator buffer
ARX
Auxiliary register value (0–7)
BITX
4-bit field specifies which bit to test for the BIT instruction
BMAR
Block-move address register
DBMR
Dynamic bit-manipulation register
I
Addressing-mode bit
II...II
Immediate operand value
INTM
Interrupt-mode flag bit
INTR#
Interrupt vector number
N
Field for the XC instruction, indicating the number of instructions (one or two) to execute conditionally
PREG
Product register
PROG
Program memory
RPTC
Repeat counter
SHF, SHFT
3/4 bit shift value
TC
Test-control bit
T P
Two bits used by the conditional execution instructions to represent the conditions TC, NTC, and BIO
T P
Meaning
0 0
BIO low
0 1
TC=1
1 0
TC=0
1 1
None of the above conditions
TREGn
Temporary register n (n = 0, 1, or 2)
Z L V C
4-bit field representing the following conditions:
Z:
ACC = 0
L:
ACC < 0
V:
Overflow
C:
Carry
A conditional instruction contains two of these 4-bit fields. The 4-LSB field of the instruction is a 4-bit mask field. A 1 in the
corresponding mask bit indicates that the condition is being tested. The second 4-bit field (bits 4–7) indicates the state of
the conditions designated by the mask bits as being tested. For example, to test for ACC
≥
0, the Z and L fields are set while
the V and C fields are not set. The next 4-bit field contains the state of the conditions to test. The Z field is set to indicate
testing the condition ACC = 0, and the L field is reset to indicate testing the condition ACC
≥
0. The conditions possible with
these 8 bits are shown in the BCND, CC, and XC instructions. To determine if the conditions are met, the 4-LSB bit mask
is ANDed with the conditions. If any bits are set, the conditions are met.
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