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參數(shù)資料
| 型號： | TMS320LC57S |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(35/50ns指令周期，并行邏輯單元，可編程PLL，全雙工同步串行口的DSP) |
| 中文描述： | 數(shù)字信號處理器（35/50ns指令周期，并行邏輯單元，可編程鎖相環(huán)，全雙工同步串行口的數(shù)字信號處理器） |
| 文件頁數(shù)： | 22/87頁 |
| 文件大?。?/td> | 1864K |
| 代理商： | TMS320LC57S |
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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
22
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
memory
The ’C5x implements three separate address spaces for program memory, data memory, and I/O. Each space
accommodates a total of 64K 16-bit words (see Figures 1 through 7). Within the 64K words of data space, the
256 to 32K words at the top of the address range can be defined to be external global memory in increments
of powers of two, as specified by the contents of the global memory allocation register (GREG). Access to global
memory is arbitrated using the global memory bus request (BR) signal.
The ’C5x devices include a considerable amount of on-chip memory to aid in system performance and
integration including ROM, single-access RAM (SARAM), and dual-access RAM (DARAM). The amount and
types of memory available on each device are shown in Table 1.
On the ’C5x, the first 96 (0–5Fh) data-memory locations are allocated for memory-mapped registers. This
memory-mapped register space contains various control and status registers including those for the CPU, serial
port, timer, and software wait-state generators. Additionally, the first 16 I/O port locations are mapped into this
data-memory space, allowing them to be accessed either as data memory using single-word instructions or as
I/O locations with two-word instructions. Two-word instructions allow access to the full 64K words of I/O space.
The mask-programmable ROM is located in program memory space. Customers can arrange to have this ROM
programmed with contents unique to to any particular application. The ROM is enabled or disabled by the state
of the MP/MC control input upon resetting the device or by manipulating the MP/MC bit in the PMST status
register after reset. The ROM occupies the lowest block of program memory when enabled. When disabled,
these addresses are located in the device’s external program-memory space.
The ’C5x also has a mask-programmable option that provides security protection for the contents of on-chip
ROM. When this internal option bit is programmed, no externally-originating instruction can access the on-chip
ROM. This feature can be used to provide security for proprietary algorithms.
An optional boot loader is available in the device’s on-chip ROM. This boot loader can be used to transfer a
program automatically from data memory or the serial port to anywhere in program memory. In data memory,
the program can be located on any 1K-word boundary and can be in either byte-wide or 16-bit word format. Once
the code is transferred, the boot loader releases control to the program for execution.
The ’C5x devices provide two types of RAM: single-access RAM (SARAM) and dual-access RAM (DARAM).
The single-access RAM requires a full machine cycle to perform a read or a write; however, this is not one large
RAM block in which only one access per cycle is allowed. It is made up of 2K-word size-independent RAM blocks
and each one allows one CPU access per cycle. The CPU can read or write one block while accessing another
block at the same time. All ’C5x processors support multiple accesses to its SARAM in one cycle as long as they
go to different RAM blocks. If the total SARAM size is not a multiple of two, one block is made smaller than 2K
words. With an understanding of this structure, programmers can arrange code and data appropriately to
improve code performance. Table 4 shows the sizes of available SARAM on the applicable ’C5x devices.
Table 4. SARAM Block Sizes
DEVICE
NUMBER OF SARAM BLOCKS
Four 2K blocks and one 1K block
’C50/’LC50
’C51/’LC51
One 1K block
’C53/’C53S /’LC53
One 2K block and one 1K block
’LC56
Three 2K blocks
’C57S/’LC57/’LC57S
Three 2K blocks
memory (continued)
The ’C5x dual-access RAM (DARAM) allows writes to, and reads from, the RAM in the same cycle without the
address restrictions of the SARAM. The dual-access RAM is configured in three blocks: block 0 (B0), block 1
(B1), and block 2 (B2). Block 1 is 512 words in data memory and block 2 is 32 words in data memory. Block 0
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