參數(shù)資料
型號(hào): TMS320LC57S
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors(35/50ns指令周期,并行邏輯單元,可編程PLL,全雙工同步串行口的DSP)
中文描述: 數(shù)字信號(hào)處理器(35/50ns指令周期,并行邏輯單元,可編程鎖相環(huán),全雙工同步串行口的數(shù)字信號(hào)處理器)
文件頁(yè)數(shù): 65/87頁(yè)
文件大小: 1864K
代理商: TMS320LC57S
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
65
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
INSTRUCTION ACQUISITION (IAQ), INTERRUPT ACKNOWLEDGE (IACK),
EXTERNAL FLAG (XF), AND TOUT (SEE NOTE 6)
switching characteristics over recommended operating conditions [H = 0.5t
c(CO)
] (see Figure 20)
PARAMETER
’320C5x-40
’320C5x-57
’320LC5x-40
’320LC5x-50
MIN
H – 12
H – 10
H – 10
’320C5x-80
’320C5x-100
’320LC5x-80
UNIT
MAX
MIN
MAX
tsu(AV-IQL)
th(IQL-AV)
tw(IQL)
td(CO-TU)
tsu(AV-IKL)
th(IKL-AV)
tw(IKL)
tw(TUH)
td(CO-XFV)
IAQ goes low during an instruction acquisition. It goes low only on the first cycle of the read when wait states are used. The falling edge should
be used to latch the valid address. The AVIS bit in the PMST register must be set to zero for the address to be valid when the instruction being
addressed resides in on-chip memory.
Valid only if the external address reflects the current instruction activity (that is, code is executing on chip with no external bus cycles and AVIS
is on or code is executing off chip)
§IACK goes low during the fetch of the first word of the interrupt vector. It goes low only on the first cycle of the read when wait states are used.
Address pins A1–A4 can be decoded at the falling edge to identify the interrupt being acknowledged. The AVIS bit in the PMST register must
be set to zero for the address to be valid when the vectors reside in on-chip memory.
NOTE 6: IAQ pin is not present on 100-pin packages.
IACK pin is not present on 100-pin and 128-pin packages.
Setup time, address valid before IAQ low
H – 9
H – 7
H – 7
ns
Hold time, address valid after IAQ low
ns
Pulse duration, IAQ low
ns
Delay time, CLKOUT1 falling edge to TOUT
Setup time, address valid before IACK low§
– 6
6
– 6
6
ns
H – 12
H – 10
H – 10
H – 9
H – 7
H – 7
ns
Hold time, address valid after IACK low
ns
Pulse duration, IACK low
ns
Pulse duration, TOUT high
2H – 12
2H – 9
ns
Delay time, XF valid after CLKOUT1
0
12
0
9
ns
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