參數(shù)資料
型號: TMS320LC57S
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors(35/50ns指令周期,并行邏輯單元,可編程PLL,全雙工同步串行口的DSP)
中文描述: 數(shù)字信號處理器(35/50ns指令周期,并行邏輯單元,可編程鎖相環(huán),全雙工同步串行口的數(shù)字信號處理器)
文件頁數(shù): 70/87頁
文件大?。?/td> 1864K
代理商: TMS320LC57S
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
70
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SERIAL-PORT TRANSMIT TIMING, EXTERNAL CLOCKS, AND EXTERNAL FRAMES
switching characteristics over recommended operating conditions (see Note 8) (see Figure 23)
PARAMETER
MIN
MAX
UNIT
td(CXH-DXV)
tdis(CXH-DX)
th(CXH-DXV)
Delay time, DX valid after CLKX high
25
40
ns
Disable time, DX invalid after CLKX high
ns
Hold time, DX valid after CLKX high
– 5
ns
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = 0.5t
c(CO)
] (see Note 8) (see Figure 23)
’320C5x-40
’320C5x-57
’320LC5x-40
’320LC5x-50
MIN
5.2H
’320C5x-80
’320LC5x-80
’320C5x-100
UNIT
MAX
MIN
5.2H
MAX
MIN
5.2H
MAX
tc(SCK)
tf(SCK)
tr(SCK)
tw(SCK)
td(CXH-FXH)
th(CXL-FXL)
th(CXH-FXL)
Values derived from characterization data and not tested
Values ensured by design but not tested
§The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching
. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
If the FSX pulse does not meet this specification, the first bit of serial data is driven on the DX pin until the falling edge of FSX. After the falling
edge of FSX, data s shifted out on the DX pin. The transmit buffer empty nterrupt s generated when the th(CXL-FXL) and th(CXH-FXL) specification
is met.
NOTE 8: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on
the source of FSX, and CLKX timings always are dependent on the source of CLKX. Specifically, the relationship of FSX to CLKX is
independent of the source of CLKX.
Cycle time, serial-port clock
§
§
§
ns
Fall time, serial-port clock
8
8
6
6
6
6
ns
Rise time, serial-port clock
ns
Pulse duration, serial-port clock low/high
2.1H
2.1H
2.1H
ns
Delay time, FSX high after CLKX high
2H – 8
2H – 8
2H – 5
ns
Hold time, FSX low after CLKX low
10
7
6
ns
Hold time, FSX low after CLKX high
2H – 8
2H – 8
2H – 5
ns
td(CXH-FXH)
DX
BIt
FSX
CLKX
8/16
7/15
2
1
th(CXH-DXV)
tw(SCK)
tr(SCK)
tf(SCK)
tw(SCK)
tc(SCK)
tdis(CXH-DX)
th(CXL-FXL)
td(CXH-DXV)
th(CXH-FXL)
Figure 23. Serial-Port Transmit Timing of External Clocks and External Frames
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