參數(shù)資料
型號(hào): TMP90CM38
廠商: Toshiba Corporation
元件分類: 通用總線功能
英文描述: High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit A/D,D/A Converter,RAM,ROM,General Serial Interface,Multifuction Timer/Event Counter,Signal Selector Circuit,PWM Output(高速、先進(jìn)的 CMOS 8位微控制器(芯片集成了8位A/D,D/A轉(zhuǎn)換器,ROM,RAM,通用串行接口,多功能定時(shí)器/事件計(jì)數(shù)器,信號(hào)選擇電路,PWM輸出))
中文描述: 采用先進(jìn)的CMOS高速8位微控制器,集成8位A / D,D / A轉(zhuǎn)換,內(nèi)存,光盤,通用串行接口,Multifuction定時(shí)器/事件計(jì)數(shù)器,信號(hào)選擇器電路,PWM輸出(高速,先進(jìn)的的CMOS 8位微控制器(芯片集成了8位A / D轉(zhuǎn)換,數(shù)/模轉(zhuǎn)換器,ROM和RAM內(nèi)存,通用串行接口,多功能定時(shí)器/事件計(jì)數(shù)器,信號(hào)選擇電路,脈寬調(diào)制輸出))
文件頁數(shù): 94/172頁
文件大?。?/td> 5946K
代理商: TMP90CM38
94
TOSHIBA CORPORATION
TMP90CM38
Capture input control circuit
This circuit controls the timing to latch the value of up-
counter UC16 into CAP1 and CAP2. The latch timing
of capture register is controlled by register T4MOD
<CAPM1,0>.
When T4MOD <CAPM1, 0> = 00
Capture function is disabled. Disable is the default on
reset.
When T4MOD <CAPM1, 0> = 01
Data is loaded to CAP1 at the rise edge of TI4 pin
(commonly used as P53/INT1) input, while data is
loaded to CAP2 at the rise edge of TI5 pin (commonly
used as P47/INT2) input. (Time difference measure-
ment)
When T4MOD <CAPM1, 0> = 10
Data is loaded to CAP1 at the rise edge of TI4 pin
input, while to CAP2 at the fall edge. Only in this set-
ting, interrupt INT1 occurs at fall edge. (Pulse width
measurement)
When T4MOD <CAP1, 0> = 11
Data is loaded to CAP1 at the rise edge of timer flip-
flop TFF1, while to CAP2 at the fall edge. (Frequency
measurement)
Besides, the value of up-counter can be loaded to
capture registers by software. Whenever “0” is written
in T4MOD <CAPIN>, the current value of up-counter
will be loaded to capture register CAP1. It is necessary
to keep the prescaler in RUN mode (TRUN <PRRUN>
to be “1”).
Comparators (CP4, CP5)
These are 16-bit comparators which compare the up-
counter UC16 value with the set value of TREG4 or
TREG5 to detect the match. When a match is
detected, the comparators generate an interrupt
INTT4 and INTT5, respectively. The up-counter UC16
is cleared only when UC16 matches TREG5. (The
clearing of up-counter UC16 can be disabled by set-
ting T4MOD <CLE> = 0.)
Timer flip-flop (TFF4)
This flip-flop is inverted by the match detect signal
from the comparators (CP4 and CP5) and the latch
signals to the capture registers (CAP1 and CAP2). Dis-
able/enable of inversion can be set for each element
by T4FFCR <CAP2T4, CAP1T4, EQ5T4, EQ4T4>.
TFF4 will be inverted when “00” is written in T4FFCR
<TFF4C1,0>. Also, it is set to “1” when “10” is written,
and cleared to “0” when “10” is written. The value of
TFF4 can be output to the timer output pin TO4 (com-
monly used as P51).
Timer flip-flop (TFF5)
This flip-flop is inverted by the match detect signal
from the comparator CP5 and the latch signal to the
capture register CAP2. TFF5 will be inverted when
“00” is written in T4FFCR <TFF5C1,0>. Also, it is set
to “1” when “10” is written, and cleared to “0” when
“10” is written. The value of TFF5 can be output to the
timer output pin TO5 (commonly used as P52).
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