參數(shù)資料
型號(hào)： TMP90CM38
廠商： Toshiba Corporation
元件分類： 通用總線功能
英文描述： High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit A/D,D/A Converter,RAM，ROM，General Serial Interface,Multifuction Timer/Event Counter，Signal Selector Circuit,PWM Output(高速、先進(jìn)的 CMOS 8位微控制器（芯片集成了8位A/D，D/A轉(zhuǎn)換器,ROM，RAM，通用串行接口，多功能定時(shí)器/事件計(jì)數(shù)器,信號(hào)選擇電路，PWM輸出）)
中文描述： 采用先進(jìn)的CMOS高速8位微控制器，集成8位A / D，D / A轉(zhuǎn)換，內(nèi)存，光盤，通用串行接口，Multifuction定時(shí)器/事件計(jì)數(shù)器，信號(hào)選擇器電路，PWM輸出（高速，先進(jìn)的的CMOS 8位微控制器（芯片集成了8位A / D轉(zhuǎn)換，數(shù)/模轉(zhuǎn)換器，ROM和RAM內(nèi)存，通用串行接口，多功能定時(shí)器/事件計(jì)數(shù)器，信號(hào)選擇電路，脈寬調(diào)制輸出））
文件頁(yè)數(shù)： 70/172頁(yè)
文件大小： 5946K
代理商： TMP90CM38
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70
TOSHIBA CORPORATION
TMP90CM38
Up-counter
This is an 8-bit binary counter that counts up the input
clock pulse specified by the timer 0/timer 1 mode reg-
ister T01MOD and timer 2/timer 3 mode register
T23MOD.
The input clock pulse for timer 0 is selected from T1
(8/fc), T4 (32/fc) and T16 (128/fc). Timer 2 input
clock is selected from external clock (TI2 pin = P55/
INT3) and same the timer 0 in three kinds internal
clock. According to the set value of T01MOD and
T23MOD.
The input clock of timer 1 and timer 3 differs depend-
ing on the operating mode. When set to 16-bit timer
mode, the overflow output of timer 0 and timer 2 is
used as the input clock.
When set to any other mode than 16-bit timer mode,
the input clock is selected from the internal clocks T1
(8/fc), T16 (128/fc), and T256 (2048/fc) as well as
the comparator output (match detection signal) of
timer 0 and timer 2, according to the set value of
T01MOD and T23MOD.
Example:When TMOD <T01M1,0> = 01, the overflow
output of timer 0 becomes the input clock of
timer 1 (16-bit timer). When TMOD <T01M1,0> =
00 and T01MOD <T1CLK1,0> = 01, T1 (8/fc)
becomes the input of timer 1.
Operation mode is also set by T01MOD and
T23MOD. When reset, it is initialized to
T01MOD <T01M1, 0> = 00 and T23MOD <T23M1,
0> = 00, whereby the up-counter is placed in the 8-bit
timer mode.
The counting, halt, and clear of up-counter can be
controlled for each interval timer by the timer operation
control register TRUN. When reset, all up-counters will
be cleared to stop the timers.
Timer registers
This is an 8-bit register for setting an interval time.
When the set value of timer register TREG0, TREG1,
TREG2, and TREG3 matches the value of up-counter,
the comparator match detect signal becomes active. If
the set value is 00H, this signal becomes active when
the up-counter overflows.
Timer registers TREG0 and TREG2 are of double
buffer structure, each of which makes a pair with reg-
ister buffer.
The TREG0 and TREG2 control whether the double
buffer should be enabled or disabled through the timer
register double buffer control register TRDC <TR0DE,
TR2DE>. It is disabled when <TR0DE>/<TR2DE> = 0,
and enabled when they are set to 1.
The timing to transfer data from the register buffer to
the timer register in the double buffer enable state is
the moment 2
- 1 overflow occurs in PWM mode or
the moment compare cycles will be equal in PPG
mode.
When reset, it will be initialized to <TR0DE, TR2DE> =
0 to disable the double buffer. To use the double
buffer, write data in the timer register, set <TR0DE>
and <TR2DE> to 1, and write the following data in the
register buffer.
n
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