參數(shù)資料
型號： TMP90CM38
廠商： Toshiba Corporation
元件分類： 通用總線功能
英文描述： High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit A/D,D/A Converter,RAM，ROM，General Serial Interface,Multifuction Timer/Event Counter，Signal Selector Circuit,PWM Output(高速、先進的 CMOS 8位微控制器（芯片集成了8位A/D，D/A轉(zhuǎn)換器,ROM，RAM，通用串行接口，多功能定時器/事件計數(shù)器,信號選擇電路，PWM輸出）)
中文描述： 采用先進的CMOS高速8位微控制器，集成8位A / D，D / A轉(zhuǎn)換，內(nèi)存，光盤，通用串行接口，Multifuction定時器/事件計數(shù)器，信號選擇器電路，PWM輸出（高速，先進的的CMOS 8位微控制器（芯片集成了8位A / D轉(zhuǎn)換，數(shù)/模轉(zhuǎn)換器，ROM和RAM內(nèi)存，通用串行接口，多功能定時器/事件計數(shù)器，信號選擇電路，脈寬調(diào)制輸出））
文件頁數(shù)： 123/172頁
文件大?。?/td> 5946K
代理商： TMP90CM38
TOSHIBA CORPORATION
123
TMP90CM38
When in SCLK1 input mode with the setting of SCCR1
<IOC1> = “1”, RxD1 signal will be sampled at the ris-
ing edge or falling edge of SCLK1 input according to
the setting of SCCR1 <SCLK1> register.
2) Asynchronous communication (UART) mode
The receiving control has a circuit for detecting the start
bit by the rule of majority. When two or more “0” are
detected during 3 samples, it is recognized as normal
start bit and the receiving operation is started.
Data being received are also evaluated by the rule of
majority.
Receiving buffer
To prevent overrun from occurring, the receiving buffer
has a double structure. Received data are stored one
bit by one bit in the receiving buffer 1 (shift register
type). When 7 bits or 8 bits of data rae stored in the
receiving buffer 1, the stored data are transferred to
another receiving buffer 2 (SCBUF1), generating an
interrupt INTRX1. The CPU reads only receiving buffer
2 (SCBUF1). Even before the CPU reads the receiving
buffer 2 (SCBUF1), the received data can be stored in
receiving buffer 1 . However, unless the receiving
buffer 2 (SCBUF1) is read before all bits of the next
data are received by the receiving buffer 1, an overrun
error occurs. If an overrun error occurs, the contents of
receiving buffer 1 will be lost, although the contents of
receiving buffer 2 and SCCR1 <RB81> is still pre-
served.
The parity bit added in 8-bit UART mode and the most
significant bit (MSB) in 9-bit UART mode are stored in
SCCR0 <RB81>.
When in the 9-bit UART, the wake-up function of the
slave controllers is enabled by setting SCMOD1
<WU1> to “1”, and interrupt INTRX occurs only when
SCCR1 <RB81> is set to “1”.
Transmission counter
Transmission counter is a 4-bit binary counter which is
used in asynchronous communication (UART) mode
and, like a receiving counter, counts by SIOCLK1
clock, generating TxDCLK1 every 16 clock pulses.
Transmission controller
1) I/O interface mode
In SCLK1 output mode with the setting of SCCR1
<IOC1> = “0”, the data in the transmission buffer are
output bit by bit to TxD1 pin at the rising edge of shift
clock which is output from SCLK1 pin.
In SCLK1 input mode with the setting of SCCR1
<IOC1> = “0”, the data in the transmission buffer are
output bit by bit to TxD1 pin at the rising edge or falling
edge of SCLK input according to the setting of SCCR1
<SCLK1> register.
2) Asynchronous communication (UART) mode
When the transmission data are written in the trans-
mission buffer sent from the CPU, transmission starts
at the rising edge of the next TxDCLK1, generating a
transmission shift clock TxDSFT1.
Hand-shake function
The TMP90CM38 supports a hand-shake function by
the connection of CTS of one TMP90CM38 and RTS0
of the other device.
The hand-shake function allows receiving/transmitting
data on a frame basis to prevent overrun errors. This
function is enabled or disabled by the control register
SCCR <CTSE>.
When the last bit (parity bit or MSB) of 1-frame data is
received by the receiving unit, the RTS pin turns to the
“H” level to request the transmission unit to halt trans-
mission.
When the CTS pin turned to the “H” level, the trans-
相關(guān)PDF資料
PDF描述
TMP90CM40 High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CUP,A/D Converter,RAM，ROM，General Serial Interface,Multifuction Timer/Event Counter(高速、先進的 CMOS 8位微控制器（芯片集成了8位CPU,A/D，轉(zhuǎn)換器,ROM，RAM，通用串行接口，多功能定時器/事件計數(shù)器）)
TMP90P800 A System Evaluation LSI With One-Time PROM(8192 x 8-Bit),RAM(256 x 8-Bit)(系統(tǒng)評估大規(guī)模集成電路（帶一次可編程ROM(8192 x 8位),RAM(256 x 8位))
TMP90P802 A System Evaluation LSI With 8-Bit CPU,One-Time PROM(8192 x 8-Bit),RAM(256 x 8-Bit)(系統(tǒng)評估大規(guī)模集成電路（集成8位CPU，一次可編程ROM(8192 x 8位),RAM(256 x 8位))
TMP90PH02 A System Evaluation LSI With 8-Bit CPU,One-Time PROM(16384 x 8-Bit),RAM(512 x 8-Bit)(系統(tǒng)評估大規(guī)模集成電路（集成8位CPU，一次可編程ROM(16384 x 8位),RAM(512 x 8位))
TMP90PH44 A System Evaluation LSI With 8-Bit CPU,One-Time PROM(16384 x 8-Bit),RAM(512 x 8-Bit)(系統(tǒng)評估大規(guī)模集成電路（集成8位CPU，一次可編程ROM(16384 x 8位),RAM(512 x 8位))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMP90CM38F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TMP90CM38T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TMP90CM39F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TMP90CM39T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TMP90CM40 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*