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參數(shù)資料
| 型號： | TDA8035HN/C1 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC32 |
| 封裝： | 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, SOT617-7, HVQFN-32 |
| 文件頁數(shù)： | 2/32頁 |
| 文件大小： | 908K |
| 代理商： | TDA8035HN/C1 |
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TDA8035HN
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1.0 — 19 April 2011
10 of 32
NXP Semiconductors
TDA8035HN
Smart card interface
8.3 Clock circuitry
To generate the card clock CLK, the TDA8035 can either use an external clock provided
on XTAL1 pin or a crystal oscillator connected on both XTAL1 and XTAL2 pins. The
TDA8035 automatically detects if an external clock is provided on XTAL1. So, there is no
need of an extra pin to configure the clock source (external clock or crystal).
The automatic clock source detection is performed on each activation command
(CMDVCCN pin falling edge). During a time window defined by the internal oscillator, the
presence of an external clock on XTAL1 pin is checked. If a clock is detected, the crystal
oscillator is kept stopped, else, the crystal oscillator is started. It is mandatory when an
external clock is used, that the clock is applied on XTAL1 before CMDVCCN falling edge
signal.
The frequency may be chosen as fXTAL, fXTAL/2, fXTAL/4 or fXTAL/8 via the pins CLKDIV1 and
CLKDIV2. (Both selection inputs shall not be changed simultaneously: 10 ns minimum are
required between changes on CLKDIV1/CLKDIV2).
The frequency change is synchronous, which means that during transition, no pulse is
shorter than 45 % of the smallest period and that the first and last clock pulse around the
change has the correct width. When changing dynamically the frequency, the change is
effective only 10 periods of XTAL1 after the command.
The duty cycle on pin CLK shall be between 45 % and 55 % :
When an external clock is used on XTAL1 pin , it should have a duty cycle of 48
% to 52 % when fXTAL is used and rise and fall times shall respect values mentioned
on table 7 tr(i), tf(i). It has to connect a 56 pF serial capacitor .
CLK frequency is fXTAL,fXTAL/2, fXTAL/4 or fXTAL/8 :
It is guaranteed between 45 % and 55 % of the period by the frequency dividers.
Fig 6.
Switch external clock
Table 4.
Clock configuration
CLKDIV1
CLKDIV2
CLK
00fXTAL/8
01fXTAL/4
11fXTAL/2
10fXTAL
001aan750
DIGITAL
MUX
Enclkin
clkxtal
XTAL
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