參數(shù)資料
型號: SX48BD
廠商: Electronic Theatre Controls, Inc.
英文描述: Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability, and On-Chip Debug
中文描述: 配置通信控制器與電子工程/閃存程序存儲器,在系統(tǒng)編程能力,以及片上調(diào)試
文件頁數(shù): 33/58頁
文件大?。?/td> 873K
代理商: SX48BD
2002 Ubicom, Inc. All rights reserved.
- 33 -
www.ubicom.com
SX48BD/SX52BD
Timer T1 Control B Register (T1CNTB)
RTCCOV
7
T1CPEDG
6
T1EXEDG
5
T1PS2-T1PS0
3
T1MC1-T1MC0
1
4
2
0
RTCCOV
RTCC Overflow Flag. This flag is automatically set to 1 when the Real-Time Clock/Counter (RTCC)
overflows from FFh to 00h. This flag stays set until it is cleared by the software. Note that this flag is not
related to multi-function timers T1 and T2.
Timer T1 Capture Edge. This bit sets the edge sensitivity of the Timer T1 input capture pins, Capture 1
and Capture 2 (RB4 and RB5). Set this bit to 1 to sense positive-going (low-to-high) edges. Clear this
bit to 0 to sense negative-going (high-to-low) edges.
Timer T1 External Event Clock Edge. This bit sets the edge sensitivity of the Timer T1 input used to
count external events (RB7). Set this bit to 1 to sense positive-going (low-to-high) edges. Clear this bit
to 0 to sense negative-going (high-to-low) edges.
Timer T1 Prescaler Divider field. This 3-bit field specifies the divide-by factor for generating the timer
clock from the on-chip system clock:
000 = divide by 1
001 = divide by 2
010 = divide by 4
011 = divide by 8
100 = divide by 16
101= divide by 32
110 = divide by 64
111 = divide by 128
For example, setting this field to 010 sets the divide-by factor to 4, which means that the T1 counter
register is incremented once every four system clock cycles.
Timer T1 Mode Control field. This 2-bit field specifies the Timer T1 operating mode as follows:
00 = Software Timer mode
01 = PWM mode
10 = Capture/Compare mode
11 = External Event mode
T1CPEDG
T1EXEDG
T1PS2-
T1PS0
T1MC1-
T1MC0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SX48BD/TQ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability, and On-Chip Debug
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