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| 型號(hào)： | SX48BD |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability, and On-Chip Debug |
| 中文描述： | 配置通信控制器與電子工程/閃存程序存儲(chǔ)器，在系統(tǒng)編程能力，以及片上調(diào)試 |
| 文件頁數(shù)： | 13/58頁 |
| 文件大小： | 873K |
| 代理商： | SX48BD |
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2002 Ubicom, Inc. All rights reserved.
- 13 -
www.ubicom.com
SX48BD/SX52BD
3.3.2 Port Configuration Registers
The port configuration registers that you control with the
MOV !rx,W instruction operate as described below.
RA through RE Data Direction Registers (MODE=1Fh)
Each register bit sets the data direction for one port pin.
Set the bit to 1 to make the pin operate as a high-imped-
ance input. Clear the bit to 0 to make the pin operate as
an output. Upon reset, the bit is set to 1.
PLP_A through PLP_E: Pullup Enable Registers
(MODE=1Eh)
Each register bit determines whether an internal pullup
resistor is connected to the pin. Set the bit to 1 to discon-
nect the pullup resistor or clear the bit to 0 to connect the
pullup resistor. Upon reset, the bit is set to 1.
LVL_A through LVL_E: Input Level Registers
(MODE=1Dh)
Each register bit determines the voltage levels sensed on
the input port, either TTL or CMOS, when the Schmitt
trigger option is disabled. Program each bit according to
the type of device that is driving the port input pin. Set the
bit to 1 for TTL or clear the bit to 0 for CMOS. Upon reset,
the bit is set to 1. If SYNC is enabled in the FUSE regis-
ter, port data must be read more than 2 cycles after a
change to the input level mode or Schmitt Trigger mode
(see Figure 3-2).
ST_B through ST_E: Schmitt Trigger Enable
Registers (MODE=1Ch)
Each register bit determines whether the port input pin
operates with a Schmitt trigger. Set the bit to 1 to disable
Schmitt trigger operation and sense either TTL or CMOS
voltage levels; or clear the bit to 0 to enable Schmitt trig-
ger operation. Upon reset, the bit is set to 1. If SYNC is
enabled in the FUSE register, port data must be read
more than 2 cycles after a change to the input level mode
or Schmitt Trigger mode (see Figure 3-2).
WKEN_B: Wakeup Enable Register (MODE=1Bh)
Each register bit enables or disables the Multi-Input
Wakeup/Interrupt (MIWU) function for the corresponding
Port B input pin. Clear the bit to 0 to enable MIWU opera-
tion or set the bit to 1 to disable MIWU operation. Upon
reset, the bit is set to 1.For more information on using the
Multi-Input Wakeup/Interrupt function, see Section 7.0.
WKED_B: Wakeup Edge Register (MODE=1Ah)
Each register bit selects the edge sensitivity of the Port B
input pin for MIWU operation. Clear the bit to 0 to sense
rising (low-to-high) edges. Set the bit to 1 to sense falling
(high-to-low) edges. Upon reset, the bit is set to 1.
WKPND_B: Wakeup Pending Flag Register
(MODE=19h)
When you access the WKPND_B register using MOV
!RB,W, the CPU does an exchange between the contents
of W and WKPND_B. Each bit read from the WKPND_B
register indicates the status of the corresponding MIWU
pin. A bit set to 1 indicates that a valid edge has occurred
on the corresponding MIWU pin, and has triggered a
wakeup or interrupt. A bit cleared to 0 indicates that no
valid edge has occurred on the MIWU pin.
CMP_B: Comparator Register (MODE=08h)
When you access the CMP_B register using MOV
!RB,W, the CPU does an exchange between the contents
of W and CMP_B. This feature lets you read the CMP_B
register contents while writing a new value to the register.
Clear bit 7 to enable operation of the comparator. Clear
bit 6 to place the comparator result on the RB0 pin. Bit 0
is a result flag that is set to 1 when the voltage on RB2
(positive input) is greater than RB1 (negative input), or
cleared to 0 otherwise. (For more information on using
the comparator, see Section 11.0.)
3.3.3 Port Configuration Upon Power-Up
Upon power-up, all the port control registers are initial-
ized to FFh. Thus, each port pin is configured to operate
as a high-impedance input that senses TTL voltage lev-
els, with no internal pullup resistor connected. The
MODE register is initialized to 1Fh, which allows immedi-
ate write access to the data direction registers using the
“
MOV !rx,W
”
instruction.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| SX48BD/TQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability, and On-Chip Debug |
| SX48BD-G | 功能描述:8位微控制器 -MCU RISC 75MHz 36I/O 262kB RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| SX48BDITQ | 功能描述:8位微控制器 -MCU TQFP UBICOM MICRO RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| SX-49-0534 | 制造商:Amphenol Corporation 功能描述: |
| SX491 | 制造商:Mallory Sonalert Products Inc 功能描述:Cap Film 91pF 500V PS 5% (7.1 X 12mm) Axial 70°C |
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