參數(shù)資料
型號: SX48BD
廠商: Electronic Theatre Controls, Inc.
英文描述: Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability, and On-Chip Debug
中文描述: 配置通信控制器與電子工程/閃存程序存儲器,在系統(tǒng)編程能力,以及片上調(diào)試
文件頁數(shù): 17/58頁
文件大?。?/td> 873K
代理商: SX48BD
2002 Ubicom, Inc. All rights reserved.
- 17 -
www.ubicom.com
SX48BD/SX52BD
4.6
FUSEX WORD (READ/PROGRAM VIA PROGRAMMING COMMAND)
4.7
DEVICE ID Word (Hard-Wired Read-Only Via Programming Command)- Part ID Code
0
0
0
0
0
10
9
8
7
6
4.8
Locations 1000h to 100Fh are allocated for user code ID.
User Code ID
IRCTRIM2 SLEEPCLK IRCTRIM1:IRCTRIM0 Unused
11
10
CF
6
BOR1:BOR0 BORTR1:BORTR0
5
4
DRT1:DRT0
1
9
8
7
3
2
0
IRCTRIM2
:
IRCTRIM0
Internal RC Oscillator Trim. This 3-bit field adjusts the operation of the internal RC oscillator to make
it operate within the target frequency range of typically 4.0 MHz. Parts are shipped from the factory
untrimmed. The device relies on the programming tool to provide trimming.
100b =
111b =
011b =
minimum frequency
Sleep Clock Disable.
0 =
enable operation of the crystal/resonator clock during power down mode (to allow fast start-
up).
1 =
disable crystal/resonator clock operation during power down mode (to reduce power con-
sumption).
Carry Flag ADD/SUB enable
0 =
carry bit input to ADD and SUB instructions.
1 =
ADD and SUB without carry
Sets the Brown Out Reset threshold voltage
00b =
4.1V
01b =
2.4V
10b =
2.2V
11b =
BOR disabled
Brown-Out trim bits (parts are shipped out of factory untrimmed).
maximum frequency
typical
SLEEPCLK
CF
BOR1: BOR0
BORTR1:
BORTR0
01b =
00 =
11 =
10b =
Delay Reset Timer (DRT) timeout period. Specifies the time from de-assertion of reset to start code
execution.
10b =
0.25 msec
11b =
18 msec
00b =
60 msec
01b =
1 sec
minimum threshold voltage
maximum threshold voltage
DRT1:DRT0
0
11
0
5
0
4
0
3
0
2
1
1
0
0
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