參數(shù)資料
型號: SX48BD
廠商: Electronic Theatre Controls, Inc.
英文描述: Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability, and On-Chip Debug
中文描述: 配置通信控制器與電子工程/閃存程序存儲器,在系統(tǒng)編程能力,以及片上調(diào)試
文件頁數(shù): 31/58頁
文件大?。?/td> 873K
代理商: SX48BD
2002 Ubicom, Inc. All rights reserved.
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www.ubicom.com
SX48BD/SX52BD
10.2.4 Capture/Compare Mode
In the Capture/Compare mode, the counter counts
upward continuously without interruption. A valid transi-
tion received on either of two input pins causes the cur-
rent value of the counter to be captured in an associated
capture register. This capture feature can be used to
keep track of the elapsed time between successive exter-
nal events. In addition, the timer continuously compares
the counter value against the value programmed into the
R1 register. Each time a match occurs, it toggles the
timer output pin, generates an interrupt (if enabled) and
sets an associated interrupt pending flag. The timer con-
tinues to count upward after a match occurs (unlike the
PWM mode, which resets the counter to zero when a
match occurs).
In the Capture/Compare mode, the timer is clocked by
the on-chip system clock divided by a value defined by a
3-bit divide-by factor. The divide-by factor can be set to
any power-of-2 from 1 to 128.
The two input capture pins are designated Capture 1 and
Capture 2. They can be configured to sense either rising
or falling edges. The Capture 1 pin captures the counter
value in a dedicated 16-bit capture register, a read-only
register. The Capture 2 pin captures the counter value in
the R2 register. The occurrence of a capture event also
generates an interrupt (if enabled) and sets an associ-
ated interrupt pending flag.
Overflow of the counter from FFFFh to 0000h also gener-
ates an interrupt (if enabled) and sets an associated
interrupt pending flag. Because the counter is free-run-
ning, an overflow can occur at any time. In cases where
the time between successive capture events might
exceed 65,536 counts of the timer, the software should
keep track of the number of overflows between succes-
sive events in order to determine the true amount of time
between such events.
10.3
Timer Pin Assignments
The following table lists the I/O port pins associated with
the Timer T1 and Timer T2 I/O functions.
Table 10-2. Timer T1/T2 Pin Assignments
10.4
There are two 8-bit control registers associated with each
timer, called the Control A and Control B registers. The
Control A register contains the interrupt enable bits and
interrupt flag bits associated with the timer. (Interrupts are
caused by comparison, capture, and overflow events.)
The Control B register contains bits for setting the timer
operating mode, the clock prescaler divide-by factor, and
the input signal edge sensitivity. Each Control B register
also contains one device configuration bit not related to
operation of the multi-function timers.
The register formats are shown in the following diagrams.
Timer Control Registers
I/O Pin
RB4
RB5
RB6
RB7
RC0
RC1
RC2
RC3
Timer T1/T2 Function
Timer T1 Capture Input 1
Timer T1 Capture Input 2
Timer T1 PWM/Compare Output
Timer T1 External Event Clock Source
Timer T2 Capture Input 1
Timer T2 Capture Input 2
Timer T2 PWM/Compare Output
Timer T2 External Event Clock Source
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