參數(shù)資料
型號(hào)： STV0299B
廠商： 意法半導(dǎo)體
英文描述： QPSK/BPSK LINK IC
中文描述： 調(diào)制/ BPSK調(diào)制連接IC
文件頁數(shù)： 8/36頁
文件大?。?/td> 242K
代理商： STV0299B
STV0299B
8/36
4
FUNCTIONAL DESCRIPTION
(continued)
4.1.5
Specific Concerns about SCL
Frequency
For reliable operation in Normal Mode, the SCL
frequency must be lower than 1/40 of the Master
Clock (M_CLK) frequency. Consequently, care
should be taken to observe the following:
1 Before returning to Normal Mode from Standby
Mode, the M_CLK frequency must be selected
such that f
M_CLK
≥
40 f
SCL
2 After Power-on reset signal, the STV0299B
operates in Normal Mode. There are two possi-
ble cases:
- DIRCLK-DIS
(pin
M_CLK = CLK_IN, the f
SCL
frequency of the
I
2
C bus must satisfy:
- DIRCLK-DIS (pin 58) is tied to V
DD
(where
frequency of the I
2
C bus must satisfy:
58)
is
grounded.
.
), and the f
SCL
and
f
SCL
≤
400 kHz.
For example, this second operating mode is
required when the application features both a
4 MHz XTAL and a 400 kHz I
2
C bus.
4.1.6
The Identification Register (at address Hex 00)
gives the release number of the circuit.
The content of this register at reset is presently A1
(same as STV0299).
Identification Register
4.1.7
The STV0299B converts the analog inputs into
digital 6-bit I and Q flows. The sampling frequency
is f
M_CLK
which is derived from an external
reference described in Section 4.1.8
‘
Clock
Generation
’
. The maximum value of f
M_CLK
is 90
MHz.
Sampling Frequency
The sampling causes the repetition of the input
spectrum at each integer multiple of f
M_CLK
. One
has to ensure that no frequency component is
folded in the useful signal bandwidth of f
S
(1+
α
)/2
where f
S
is the symbol frequency, and
α
is the
roll-off value.
4.1.8
An integrated VCO (optimised to run in the range
of 300 to 400 MHz) is locked to a reference
frequency provided by a crystal oscillator by the
following relation:
Clock Generation
The VCO
’
s loop filter is optimized for a reference
frequency between 4 and 8 MHz.
The VCO generates the following by division:
The Master Clock (M_CLK)
An auxiliary clock (AUX_CLK) which may either
be in the MHz range or in the 25 Hz to 1500 Hz
range for some specific LNB control (for
example, 60 Hz).
A lower frequency, F22, typically 22 KHz,
needed for LNB control or DiSEqC
TM
control.
When DIRCLK_CTRL = 1, the crystal signal is
routed directly to M_CLK; the VCO may still be
used to generate AUX_CK and/or the F22 (used
by the DiSEqC
TM
interface).
If the internal VCO is not used by any of the
dividers, it may be stopped in order to decrease
the
power
consumption
emissions. The only guaranteed function in
standby mode is the I
2
C Write/Read function of
the three clock control registers.
There are restrictions on the high and low level
durations, and on the crystal (or external clock)
frequency when the direct clock is used.
These restrictions are explained in Section 4.1.5
Specific Concerns about SCL Frequency.
and/or
radiation
f
SCL
--------------------
≤
f
M_CLK
---------
f
CLK_IN
=
f
SCL
-------------------
CLK_IN
≤
f
VCO
f
ref
4
M
1
+
(
)
f
XTAL
4
K
1
1
+
-----+
=
=
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