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參數(shù)資料
| 型號(hào)： | STV0299B |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | QPSK/BPSK LINK IC |
| 中文描述： | 調(diào)制/ BPSK調(diào)制連接IC |
| 文件頁數(shù)： | 27/36頁 |
| 文件大?。?/td> | 242K |
| 代理商： | STV0299B |
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STV0299B
5
REGISTER LIST
(continued)
27/36
RS CONTROL REGISTER
(refer to Section 4.6.6
on page 16
)
RS
33
F8
7
RS7
- Deinterleaver Enable
1: The input flow is deinterleaved.
0: The input flow is not affected.
6
RS6
- Synchro Enable
1: The synchro is processed.
0: The synchro word search is disabled. The bit-to-byte conversion
remains in its current phase regardless of whether the synchro
word is recognized or not. This allows the use of the STV0299BB
with
inner convolutional coding only.
5
RS5
- Reed-Solomon Enable
1: The input code is corrected.
0: No correction happens, all the data is fed to the descrambler.
The error signal remains inactive.
4
RS4
- Descrambler Enable
1: The output flow from Reed-Solomon decoder is descrambled.
0: The descrambler is disactivated.
3
RS3
- Write Error Bit
1: If an uncorrectible error happens in DVB, the MSB of the first byte
following the sync byte is forced to 1 after descrambling.
0: The output flow is unchanged.
2
RS2
- Block Synchro
1: The first byte of each packet is forced to Hex 47 in mode A.
0: The first byte is the one that is received. In DVB, it should be the
synchro byte, complemented every 8th packet.
1
RS1
- Output Clock Polarity
1: The data and control signals are clocked during the high-to-low
transition of CLK_OUT.
0: The data and control signals are clocked during the low-to-high
transition of CLK_OUT.
0
RS0
- Output Clock Signal Configuration during Parity Bytes
1: D[7:0] and ERROR are null during the parity bytes. If the packet
contains more than 8 errors, ERROR only remains high during the
data transmission. In parallel mode, CLK_OUT remains low during
the parity bytes. In serial mode, the output bit clock is always
running.
0: CLK_OUT is continuous and the parity bytes are transmitted. If the
packet contains more than 8 errors, ERROR remains high during
the entire packet.
Name
HEX
Address
Reset
Value
Bit
Position
Signal Description
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相關(guān)代理商/技術(shù)參數(shù) |
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