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參數(shù)資料
| 型號： | STV0299B |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | QPSK/BPSK LINK IC |
| 中文描述： | 調(diào)制/ BPSK調(diào)制連接IC |
| 文件頁數(shù)： | 7/36頁 |
| 文件大?。?/td> | 242K |
| 代理商： | STV0299B |
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STV0299B
7/36
4
FUNCTIONAL DESCRIPTION
The STV0299B is a multistandard demodulator
and error correction decoder IC for the reception
of QPSK and BPSK modulated signals. It is
intended for use in digital satellite television
applications. The IC can accept two standards of
QPSK modulated signals (DVB and DSS) as well
as BPSK modulated signals over a wide symbol
frequency range (from 1 to 50 Msymbols/s). The
signals are digitized via an integrated dual 6-bit
analog to digital converter, and interpolated and
digitally filtered by a Nyquist root filter (with a
settable roll-off value of either 0.35 or 0.20).
There are two built-in digital Automatic Gain
Controls (AGCs). The first AGC allows the tuner
gain to be controlled by the pulse density
modulated output. The second AGC performs
power optimization of the digital signal bandwidth
(internal to the STV0299B). The digital signal then
passes through the digital carrier loop fitted with
an on-chip derotator and tracking loop, lock
detector, and digital timing recovery.
Forward error correction is integrated by way of an
inner Viterbi soft decoder, and an outer
Reed-Solomon decoder.
4.1 Front End Interfaces
4.1.1
The standard I
2
C protocol is used whereby the
first byte is Hex D0 for a write operation, or Hex
D1 for a read operation. The I
2
C interface
operates differently depending on whether it is in
normal or standby mode.
I
2
C Interface
4.1.2
The byte sequence is as follows:
1 The first byte gives the device address plus the
direction bit (R/W = 0).
2 The second byte contains the internal address
of the first register to be accessed.
3 The next byte is written in the internal register.
Following bytes (if any) are written in
successive internal registers.
4 The transfer lasts until stop conditions are
encountered.
5 The STV0299B acknowledges every byte
transfer.
Write Operation (Normal Mode)
4.1.3
The address of the first register to read is
programmed in a write operation without data, and
terminated by the stop condition. Then, another
start is followed by the device address and R/
W = 1. All following bytes are now data to be read
at successive positions starting from the initial
address. Figure 2 shows the I
2
C Normal Mode
Write and Read Registers.
Read Operation (Normal Mode)
4.1.4
Only three registers can be addressed while in
standby mode: RCR (address 01 Hex), MCR
(address 02 Hex) and ACR (address 03 Hex).
These three registers can be either read or written
to (refer to Figure 3).
Only one register may be read or written to per
sequence (no increment). While in standby mode,
the Serial Clock (SCL) frequency must be lower than
one tenth of the CLK_IN frequency (f
CLK_IN
/ 10).
I
2
C Interface in Standby Mode
Figure 2:
Write registers 0 to 3 with AA, BB, CC, DD
I
2
C Read and Write Operations in Normal Mode
Figure 3:
Write operation
I
2
C Read and Write Operations in Standby Mode
Read registers 2 and 3
Start
Device
Address,
Write D0
ACK
Register
Address
00
ACK
Data
AA
ACK
Data
BB
ACK
Data
CC
ACK
Data
DD
ACK
Stop
Start
Device Address, Write D0
ACK
Register Address 02
ACK
Stop
Start
Device Address,
Read D1
ACK
Data Read CC
ACK
Data Read DD
ACK
Stop
Read operation
Start
Device Address, Write D0
ACK
Register Address 01, 02 or 03
ACK
Data
ACK
Stop
Start
Device Address
, Read D0
ACK
Register Address
ACK
Stop
Start
Device Address,
Read D1
ACK
Reader Data
ACK (or no
ACK
1
)
Stop
Note: 1 ACK is not absolutely necessary after Data
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