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參數(shù)資料
| 型號(hào)： | STV0299B |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | QPSK/BPSK LINK IC |
| 中文描述： | 調(diào)制/ BPSK調(diào)制連接IC |
| 文件頁(yè)數(shù)： | 5/36頁(yè) |
| 文件大?。?/td> | 242K |
| 代理商： | STV0299B |
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STV0299B
5/36
1
PIN INFORMATION
(continued)
1.2 Pinout Description
Pin Number
Note:
1
2
3
The following abbreviations are used: I - Input; O - Output; OD - Open drain output.
3.3 V output levels.
5 V tolerant
Name
I/O
1
Description
SIGNAL INPUTS
50, 51
53, 54
IP, IN
QN, QP
I
I
Analog in Phase Component
Analog in Quadrature Component
FRONT END CONTROLS
CLK_IN/XTAL IN
I
Crystal Input or CLK_IN
XTAL OUT
O
Crystal Output
OD
3
Control Signal to the Tuner
O
2
Programmable Output Port or Programmable Output Clock
O
2
Programmable Output Ports
O
2
Carrier Found or Data Found or Output Port
IP0
I
Input Port
1
2
9
AGC
5
AUX_CLK
17-18
OP0, OP1
19
LOCK/OP2
38
SIGNAL OUPUTS
26-28-29-31, 33 to 36
D[7:0]
O
2
O
2
O
2
O
2
O
2
I
2
C INTERFACE
I
3
Serial Clock (I
2
C bus)
I/OD
3
Serial Data (I
2
C bus)
Output Data; D7 is DATA_OUT in Serial Mode
24
CLK_OUT
Output Byte Clock; or Bit Clock in Serial Mode
22
STR_OUT
Output 1st byte Signal (synchro byte clock)
21
D/P
Data/Parity Signal
20
ERROR
Output Error Signal. Set in case of uncorrectible packet.
14
SCL
12
SDA
OTHERS
59
SCLT
OD
3
I/OD
3
Tuner Serial Clock (repeator) or Output Port
60
SDAT
Tuner Serial Data (repeator) or Input/Output Port
37-43-44-45-46-61-62
TEST
I
Reserved for manufacturing tests; must be tied to V
SS
Sets the DIRCLK function at power on
58
DIRCLK_DIS
V
SSA
V
DDA
V
TOP
V
BOT
V
SS
V
DD_3.3 V
V
DD
RESET
STDBY
I
3, 49, 52, 57
S
Analog Ground
4, 47, 55
S
Analog 2.5 V Supply
56
S
ADC High Voltage Reference
48
S
ADC Low Voltage Reference
6-8-11-23-27-32-39-64
S
Ground
13-25
S
3.3 V Supply
7-10-30-41-63
S
2.5 V Supply
15
42
I
I
Reset, active at low level
Sets STDBY at power on
DiSEqC modulation, 22 kHz Tone, Programmable
Output Port
16
F22/DiSEqC
O
2
40
DAC
O
2
Programmable Digital to Analog Converter Output
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