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參數(shù)資料
| 型號： | STV0299B |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | QPSK/BPSK LINK IC |
| 中文描述： | 調(diào)制/ BPSK調(diào)制連接IC |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 242K |
| 代理商： | STV0299B |
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STV0299B
5
REGISTER LIST
(continued)
22/36
INPUT/OUTPUT CONFIGURATION REGISTER
(refer to Section 4.2.1
on page 12
)
IOCFG
0C
F0
7
OP1 control
1: Open drain
0: Normal
6
OP1 value
5
OP0 control
1: Open drain
0: Normal
4
OP0 value
3
This bit must be programmed to zero.
[2:1]
Nyquist Filter
These bits determine Nyquist filter settings:
00 = raised cosine at 35%
01 = raised cosine at 20%
10 = reserved
11 = reserved
0
Bit 0 when set, multiplies the data on the Q input by -1 in order to
accommodate QPSK modulation with another convention of rotation
sense. This is equivalent to a permutation of I and Q inputs, or a spec-
tral symmetry. This permutation is performed after derotation.
AGC1 CONTROL REGISTER
(refer to Section 4.2.2
on page 12
)
AGC1C
0D
81
7
DC offset compensation:
1: On
0: Off
[6:3]
These bits must be programmed to zero.
[2:0]
beta_agc1
TIMING LOOP REGISTER
(refer to Section 4.3.1
on page 13
)
RTC
0E
23
7
This bit must be programmed to zero.
[6:4]
alpha_tmg
3
This bit must be programmed to zero.
[2:0]
beta_tmg
AGC1 REFERENCE REGISTER
(refer to Section 4.2.2
on page 12
)
AGC1R
0F
54
7
Iagc
1: Invert
0: Normal
If Iagc is set, the output signal is complemented (i.e. a high value for
the AGC voltage will cause a high gain in the tuner).
6
This bit must be programmed to zero.
[5:0]
AGC1 Reference Value (m1).
Refer to page 12.
AGC2 AND OFFSET CONTROL REGISTER
(refer to Section 4.2.5
on page 12
)
AGC2O
10
74
[7:5]
AGC2 Coefficient
[4:0]
AGC2_Ref (m2)
Name
HEX
Address
Reset
Value
Bit
Position
Signal Description
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