參數(shù)資料
型號(hào)： STV0299B
廠商： 意法半導(dǎo)體
英文描述： QPSK/BPSK LINK IC
中文描述： 調(diào)制/ BPSK調(diào)制連接IC
文件頁(yè)數(shù)： 31/36頁(yè)
文件大小： 242K
代理商： STV0299B
STV0299B
31/36
6
ELECTRICAL CHARACTERISTICS
(continued)
6.4 Timing Characteristics
Note:
1
Tm = Master clock period in ns
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Symbol
Parameter
Min.
Typ.
Max.
Unit
f
VCO
f
CLK_IN
PARALLEL OUTPUT D[7:0], D/P, CLK_OUT, STR_OUT, ERROR OUTPUT CHARACTERISTICS
Bit RS1 = 1 in RS CONTROL REGISTER (Address 33). Refer to Figure 8
t
CLK_duty
CLK_OUT duty cycle
D[7:0], D/P STR_OUT, ERROR stable before CLK_OUT
Falling Edge
D[7:0], D/P, STR_OUT, ERROR stable after CLK_OUT
Falling Edge
Internal VCO frequency
CLK_IN or XTAL frequency
300
4
400
30
MHz
MHz
40
50
60
%
t
CKSU
2*Tm
(1)
ns
t
CKH
2*Tm
(1)
ns
Bit RS1 = 0 in RS CONTROL REGISTER (Address 33). Refer to Figure 9
D[7:0], D/P STR_OUT, ERROR stable before CLK_OUT
Falling Edge
D[7:0], D/P, STR_OUT, ERROR stable after CLK_OUT
Falling Edge
SERIAL OUTPUT D7, D/P, CLK_OUT, STR_OUT, ERROR OUTPUT CHARACTERISTICS
Bit RS1 = 1 in RS CONTROL REGISTER (Address 33). fM.CLK = 90MHz. Refer to Figure 10
D7, D/P, STR_OUT, ERROR stable before CLK_OUT
Falling Edge
D7, D/P, STR_OUT, ERROR stable after CLK_OUT
Falling Edge
t
CKSU
2*Tm
(1)
ns
t
CKH
2*Tm
(1)
ns
t
CKSU
3.5
ns
t
CKH
3
ns
Bit RS1 = 0 in RS CONTROL REGISTER (Address 33). fM.CLK = 90MHz. Refer to Figure 11
D7, D/P, STR_OUT, ERROR stable before CLK_OUT
Falling Edge
D7, D/P, STR_OUT, ERROR stable after CLK_OUT
Falling Edge
t
CKSU
3.5
ns
t
CKH
2
ns
CLK_OUT
D[7:0], D/P.
STR_OUT,
ERROR
t
CKH
t
CKSU
CLK_OUT
D[7:0], D/P.
STR_OUT,
ERROR
t
CKH
t
CKSU
CLK_OUT
D7, D/P.
STR_OUT,
ERROR
t
CKH
t
CKSU
CLK_OUT
D7, D/P.
STR_OUT,
ERROR
t
CKH
t
CKSU
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