
STV0299B
5
REGISTER LIST
(continued)
20/36
AUXILIARY CLOCK REGISTER
(refer to Section 4.1.8
on page 8
)
ACR
03
2A
[7:0]
ACR Prescaler and Divider
This register is made up of the ACR [7:5] Prescaler field and the ACR
[4:0] Divider field. The values in these fields configure the auxiliary
clock function, the prescalar value, the clock signal frequency.
The frequency range is given for f
VCO
= 400 MHz.
ACR [7:0]
Function
Prescaler
Signal Frequency
Range
000XXXX0
Output
Port
N/A
output port = 0
N/A
000XXXX1
Output
Port
N/A
output port = 1
N/A
001XXXXX
HF
generator
1
f
VCO
/8/ACR[4:0]
1.6 to
50 MHz
010XXXXX
LF
generator
64
f
VCO
/8192/(32+ACR[4:0])
775 to
1525 Hz
011XXXXX
LF
generator
128
f
VCO
/16384/(32+ACR[4:0])
388 to
762 Hz
100XXXXX
LF
generator
256
f
VCO
/32768/(32+ACR[4:0])
194 to
381 Hz
101XXXXX
LF
generator
512
f
VCO
/65536/(32+ACR[4:0])
97 to
190 Hz
110XXXXX
LF
generator
1024
f
VCO
/131072/(32+ACR[4:0])
49 to
95 Hz
111XXXXX
LF
generator
2048
f
VCO
/262144/(32+ACR[4:0])
24 to
47 Hz
In the LF generator, the programmable division factor is
32 + ACR[4:0]. In the HF generator, it is simply ACR[4:0]. This allows
the building of any frequency from 24 Hz to 1.1 kHz (within ±1.5%) in
the full operating range. The output signal is square in all cases.
When the auxiliary register is written, the prescaler and the program-
mable divider are reset.
F22 FREQUENCY REGISTER
(refer to Section 4.1.8
on page 8
)
F22FR
04
8E
[7:0]
The actual frequency is f
VCO
/(128 R[7:0]). When this register is
accessed, the divider by 16 (also common to AUX_CLK) and the
divider by R[7:0] are initialized.
I
2
CRPT REGISTER
(refer To Section 4.1.10
on page 10
)
I
2
CRPT
05
0F
7
I
2
CT
1: I
2
C repeater
0: Output port
[6]
Must be programmed to zero.
[5:4]
Repeater response time; value does not matter if the external time
constant
≤
250ns.
[3]
Must be programmed to zero.
2
SCLT Port value
1
This bit must be programmed to zero.
0
SDAT Port value
Name
HEX
Address
Reset
Value
Bit
Position
Signal Description