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參數(shù)資料
| 型號(hào)： | STLC5048 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | Codec |
| 英文描述： | FULLY PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER |
| 中文描述： | 完全可編程四通道解碼器和過濾器 |
| 文件頁數(shù)： | 6/45頁 |
| 文件大?。?/td> | 371K |
| 代理商： | STLC5048 |
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STLC5048
6/45
No.
Name
Type
Description
28
CS0
DIO
Slic CS control #0. Depending on CONF reg. content can be a CS
output for SLIC #0 or a static I/O.
When configured as CS output it is automatically generated by the
CODEC with a repetition time of 31.25ms. In this mode also the
IO0..11 are synchronised and carry proper data in and out
synchronous with CS.
When configured as static I/O, the direction is defined by CSDIR
register content.
29
CS1
DIO
Slic CS control #1, (see CS0 description).
53
CS2
DIO
Slic CS control #2, (see CS0 description).
52
CS3
DIO
Slic CS control #3, (see CS0 description).
4
CS
DI
Chip Select Input, when this pin is low control information can be
written to or read from the device via the CI and CO pins.
7
CCLK
DI
Clock of Serial Control Bus. This clock shifts serial control information
into or out of CI or CO when CS input is low depending on the current
instruction. CCLK may be asynchronous with the other system
clocks.
6
CI
DI
Control Data Input of Serial Control Bus.
Control data is shifted in the device when CS is low and clocked by
CCLK. Depending on the addressed register different numbers of
consecutive bytes can be loaded.
5
CO
DI
Control Data Output of Serial Control Bus.
Control data is shifted out the device when CS is low and clocked by
CCLK. Depending on the addressed register different numbers of
consecutive bytes can be shifted out.
3
INT
ODO
Interrupt output (open drain), goes low when a data change has been
detected in the I/O pins or another interrupt source is active. One
mask register allows to mask any I/O pin. Interrupt is reset when the I/
O register is read.
17
TSXB
ODO
Transmit Time Slot (open drain output, 3.2mA). Normally it is floating
in high impedance state except when a time slot is active on the DXB
output. In this case TSXB output pulls low to enable the backplane
line driver.
15
DXB
DTO
Transmit PCM interface B. It remains in high impedance state except
during the assigned time slots during which the PCM data byte is
shifted out on the rising edge of MCLK.
16
DRB
DI
Receive PCM interface B. It remains inactive except during the
assigned receive time slots during which the PCM data byte is shifted
in on the falling edge of MCLK.
PIN DESCRIPTION
(continued)
DIGITAL PIN DESCRIPTION (continued
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STLC5048TR | 功能描述:接口—CODEC Prog 4-Ch CODEC/Filt RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| STLC5411 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE |
| STLC5411CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN Line Interface |
| STLC5411FN | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE |
| STLC5411P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE |
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